As a part of ad9361 integration efforts we are testing the reference ZedBoard / AD-FMCOMMS2-EBZ platform.
The default SPI speed of the ad9361 device on this platform is 10MHz. While this works fine, for various reasons we need to use faster SPI transfers.
As AD9361 Reference Manual UG-570 states that
The maximum SPI_CLK frequency is 50 MHz.
we tried to raise SPI speed to 50MHz to verify such claim.
To our great surprise the highest SPI speed that seems to works reliably is 40MHz: above that limit the driver is unable even to create valid sysfs entries.
SPI speed modification method
Linux version 4.6.0-gca4cf2a (jenkins@romlx1) (gcc version 4.8.3 20140320 (prerelease) (Sourcery CodeBench Lite 2014.05-29) )#21 SMP PREEMPT Mon Nov 21 14:17:49 GMT 2016
Could you please explain why the SPI frequencies above 40MHz do not work?
Do we need to change anything in ad9361 SPI configuration for 40+ MHz frequencies to work?
Does ad9361 really support 50MHz SPI transfers?
Thank you in advance,
I was trying to find this information from the ZedBoard's devicetree, but I could not find it after looking briefly.
Do you have any idea what's the max speed that the ZedBoard's SPI controller can handle ?
A lot of the reference designs which we provide (including FMCOMMS2) are typically tested on ZC706/ZCU102 which are faster systems.
Generally speaking, the question "Does ad9361 really support 50MHz SPI transfers?" should be addressed to another forum.
Particularly this one:
They should be able to answer this question more thoroughly as well as provide more insight as to achieving that SPI speed.
thanks for the reply, I will post the question in the forum you suggest.
ZedBoard is based on Xilinx Zynq®-7000 SoC. Zynq-7000 SoC Technical Reference Manual UG585 in chapter 17.1.1 states (in SPI features)
50 MHz SCLK clock frequency when I/O signals are routed to the MIO pins25 MHz SCLK when the I/O signals are routed via the EMIO interface to the PL pins
As 40MHz frequency works it should be that /O signals are routed to the MIO pins and thus 50MHz should work too.
Our project routes the SPI through EMIO interface, as that's the only way we can connect to the FMC connector.
Does it mean that if EMIO would be replaced to MIO, ad9361 would work stable 50MHz SPI?Does ADI has a reference EVK / platform where ad9361 can achieve 50MHz SPI speed?
I'm not aware of any platforms with AD9361 at 50MHz. Maybe somebody from https://ez.analog.com/wide-band-rf-transceivers/design-support/ knows in which conditions AD9361 SPI should work at 50MHz.
You could try replacing the EMIO SPI with AXI QUAD SPI, which may be faster from the logic point of view, but it doesn't guarantee it would work, given that the signals are routed through the zedboard, FMC connector and fmcomms2 and I don't think trace length matching was taken into consideration for the SPI connection.
https://wiki.analog.com/resources/eval/user-guides/adrv936x_rfsom doesn't have an FMC connection between the FPGA and the AD9361 so it has a higher chance for the SPI connection to work at maximum speed.