ADALM PLUTO clk custom IP


I'm Alex. I'm using the Adalm Pluto board for a SDR application and I wanted to substitute the Interpolator IP in the Vivado design for a custom VHDL IP. This new IP will also get the data from the DMA and send it to the AXI_AD9631 core. My questions are related with the use of the sampling frequency configuration using libiio. 

As I think, when you configure the DAC sampling frequency in the transceiver (using the ad9361_phy libiio device), you are also configuring this value in the AXI_AD9631 core and its generate a l_clk signal with the desirable sample rate to manage the interpolator and dma controller clk. Is it that correct? How the DMA controller knows that the interpolation factor is 8 and change its read frequency?. Also I think that the interpolator block knows about this configuration reading from up_dac_gpio_out port. I found in your wiki these registers are used to know the changes in the driver configuration. Is there any information about what does every bit mean?

Moreover, is there any information about the hardware changes when you configure the drivers from Linux? is there also information about how to modify those drivers with custom parameters? 

Thanks in advance.