ADRV9009 no-OS, different bit positions for TX_TPC_CONFIG register between no-OS and Linux driver code

From the TALISE_initialize() function in talise.c, no-OS has this:

/* Enable SPI Tx Atten mode and set Atten step size. Only write bottom 6 bits */
regData = 0;
regData |= TPC_MODE_TX1_SPI;
regData |= TPC_MODE_TX2_SPI;
regData |= (init->tx.txAttenStepSize << 4);
halError = talSpiWriteField(device->devHalInfo, TALISE_ADDR_TX_TPC_CONFIG,
regData, 0x3F, 0);

While the Linux driver has this:

/* Enable SPI Tx Atten mode */
halError = talSpiWriteField(device->devHalInfo, TALISE_ADDR_TX_TPC_CONFIG, 0x01, 0x03, 0);
retVal = talApiErrHandler(device,TAL_ERRHDL_HAL_SPI, halError, retVal, TALACT_ERR_RESET_SPI);
IF_ERR_RETURN_U32(retVal);

halError = talSpiWriteField(device->devHalInfo, TALISE_ADDR_TX_TPC_CONFIG, 0x01, 0x0C, 2);
retVal = talApiErrHandler(device,TAL_ERRHDL_HAL_SPI, halError, retVal, TALACT_ERR_RESET_SPI);
IF_ERR_RETURN_U32(retVal);

Either the txAttenStepSize bits are shifted over 2 bits too far, or the Linux driver is wrong.