The point is I would like to want how long the SPI wires can be if this bus is
isolated by an ADUM1401 ?
It is a very simple bus, and the answer depends on the data rate.
They need to guarantee data from the slave device is stable at the master
before the complementary clock edge is issued.
That means that the returning data is 2 propagation delay times behind the
initial clock edge.
What goes into this is the delay time of the coupler and the line capacitance.
If they are going to design for maximum data rate, then they can use the
guaranteed timing specifications for our device if the line and load
capacitance is kept under 15pF.
This will set the maximum trace length.
If they are running lower data rates, then the traces can be longer.
Longer traces with higher capacitance will slow down the slew rate of the
outputs causing more propagation delay.
So there will be a tradeoff between speed and trace length (trace