The issue is likely caused by updating critical registers (such as baud rate and clock settings) on MAX14830 while the receiver is actively receiving data. Changing these settings during data reception can cause the receiver to miss bits or frames, resulting in the RX FIFO locking up.
Some recommendations that can be followed to prevent this from happening are given below:
- Avoid updating critical registers (e.g., baud rate and clock settings) while the receiver is receiving data. Ensure the device is fully configured before enabling the receiver or allowing data to be received.
- As a workaround during initialization:
- Perform a software reset via the appropriate control register.
- Immediately disable the receiver after the reset, before the RX FIFO can overflow.
- Clear the FIFO using the FIFO reset control.
- Configure all necessary registers while the receiver is disabled.
- Re-enable the receiver as the final step after configuration is complete.
- To further enhance robustness and prevent RX FIFO overflow:
- Use AutoRTS control to manage flow control. Configure HALT and RESUME levels to set thresholds for asserting and de-asserting RTS, providing hysteresis for transitions.
- Configure the RxTrig bits to define the RX FIFO threshold level at which an interrupt is generated, allowing timely reading of the FIFO before overflow.
- Use the receive holding register (RHR) to read out the receive FIFO when an interrupt is generated.
- Consider using 2x or 4x baud rate modes via the baud-rate generator configuration register to support higher baud rates if needed.
- Poll the FIFO state and read data at regular intervals (e.g., every 1 ms) to ensure the RX FIFO does not overflow.
- Do not update baud rate or other critical settings while data is present on the RX line to avoid potential lock-up scenarios.