When the voltage on VDD input side falls below the device specification, the outputs oscillate with sporadic or continuous bursts of pulses which could confuse the end device or the receiver processor. However, this behavior is normal & expected. These pulses are sent to ensure DC correctness as explained in the datasheet, i.e. In the absence of logic transitions of more than ~1 μs at the input when VDD1 or the input side is unpowered, periodic refresh pulses are sent to indicate the correct input state. If the decoder receives no internal pulses for more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, and the isolator output is forced to a default state by the watchdog timer circuit. If this behavior is not desired, the customers may select another isolator with a different architecture that does not exhibit the same behavior and comes in an equivalent pin-compatible SOIC8 package. Recommended alternatives include:
- MAX22420: Reinforced, Ultra-low power MAX22420, MAX22421, MAX22820, MAX22821 - Reinforced, Ultra-Low-Power, Two-Channel Digital Isolators
- ADUM320N: Fail-safe option with default high/low, uses the OOK (On-Off Keying) architecture ADUM320N Datasheet and Product Info | Analog Devices
- ADUM120N: Uses OOK as well and does not use a watchdog timer. ADuM120N | datasheet and product info Robust 3.0 kV rms Dual Channel Digital Isolator & 0 Reverse Channels | Analog Devices