What is the theoretical number limit of MAX22196 chips connected in a daisy chain?

Theoretically there is no limit on how many MAX22196 can be daisy chained. When the MAX22196 is configured in the daisy chain mode, the shift registers on the SDI and SDO receives the data from the previous device in the chain and passes along the data to the next device in the chain as long as the correct number of SCLK pulses are received and CS_N is kept low. When all the devices receive its respective data and the CS_N is pull high, each MAX22196 in the chain executes the data command stored in the shift register. During next time CS_N is set low, every MAX22196 sends data through SDO. The data get passed along the chain back to the MCU or FPGA when the correct number of SCLK pulses are received and CS_N is kept low.

For each of MAX22196 in the chain, it does not care how many devices in the daisy chain. It only passes along the data when CS_N is low, executes the command it receives at the end when CS_N is pulled high, and sends out the data when the CS_N is pulled low.

In a real implementation, if a large number of devices are connected in daisy chain, the following things need to be considered:

1. CS_N and SCLK need to be received correctly by every MAX22196 in the chain. With for example, 100 devices in the system, the signal could be distorted at far end of the transmission line. Adding buffers is an option, but buffer adds delay. The customers need to make sure every MAX22196 samples the right data bit at SDI on the rising edge of the SCLK and sends out the data at SDO on the corresponding falling edge of the SCLK.
2. The first device in the daisy chain receives SDI from SPI master (MCU or FPGA). The last device in the daisy chain sends SDO to SPI master (MCU and FPGA). These could be fairly long transmission line as well.
3. For the middle devices in the chain, SDI is connected to the previous device in the chain and SDO is connected to the next device in the chain, so there will be less concerns about signal integrity.
4. With a large number of devices in the chain, the command delay is significantly longer. In the case of for example 100 devices in the chain, one command for each device takes 24 bits, assuming SCLK frequency is 10MHz, one command for one device takes 2.4us, commands for 100 devices take 240us. This mean it takes 240us for the commands to reach its respective device. This makes DI reading delay or fault reading delay longer. It would also depend on the customer application whether it can afford this delay.