As soon as V5 exceeds V5_POR threshold (2.4V max) the device is ready for communication via SPI. However, all outputs, O_, are in tri-state (Hi-Z) until V5 below its UVLO level (4.2V max) and VDD is below its UVLO level (8.5V max). The output will be released (follow the register settings) only when each supply exceeds their UVLO levels. By default the outputs are off (Hi-Z) when in high-side mode or low in push-pull mode.