On the MAX9275, the number is simply how much jitter the 30/40x PLL can tolerate. On the MAX9277, the clock is PCLK rate, but the data is 7xPCLK. There is a 7xPLL on RXCLKIN, which is used to generate a clock to recover parallel data from oLDI data. That means this PLL cleans the clock, but since the input clock was generated from the same chip as the data, that can make things worse.
Let’s say the data and clock were both jittery (as they come from the same source). Then, you clean the clock with the 7xPLL. Now the data looks jittery compared to the clean clock, and we try to use that clock to recover the jittery data. The result is that you need to consider the jitter as related to 7xPCLK, whereas in the MAX9275 it is related to PCLK. You can assume the 7xPLL completely cleans the clock and then needs to recover the data, so the data must be within +/- 0.5 of a data bit for the clean clock to recover it. A typical way to allocate this jitter allowance is half for clock jitter and half for data jitter, so you can say the max clock jitter is +/- 0.25 of a data bit (one data bit is 1/(PCLKx7, if PCLK is 100MHz, one data bit is 1.4ns and 0.25 of a data bit is 350ps).