To clarify, TxSynch is not a global register. It needs to be written separately for each individual UART.
For example, to set CLKtoGPIO for all four UARTs, the sequence should be as follow:
1. Write to the Global Command Register to enable extended register map access(0xCE)
2. Write to UART0(Table 11: U1 =0, U0 = 0) and set the CLKtoGPIO bit of the TxSynch register to 1.
3. Write to UART1(Table 11: U1 =0, U0 = 1) and set the CLKtoGPIO bit of the TxSynch register to 1.
4. Write to UART2(Table 11: U1 =1, U0 = 0) and set the CLKtoGPIO bit of the TxSynch register to 1.
5. Write to UART3(Table 11: U1 =1, U0 = 1) and set the CLKtoGPIO bit of the TxSynch register to 1.
6. Write to the Global Command Register to disable extended register map access(0xCD) if you no longer need extended register map access.
As a side note, the synchronization register can also be used to configure the UARTs such that multiple UARTs may start transmission simultaneously (if TxFIFO contains data) when a global trigger command is received. The global trigger command is transmitted via the Global Command Register. (pg 54 of the datasheet). For example, if TxSynch register of UART0 and UART1 has D0-D3(TrigSel0 to TrigSel3) set to 0x8 and SynchEn set to 1, writing 0xE8 to Global Command Register will trigger UART0 and UART1.