The MAX3420E interrupt request bits are cleared by writing "1" to them. Is this backwards?

It may seem backwards at first, but it is the most efficient way to clear a register bit. To service a typical interrupt request, the SPI master reads an interrupt request register (either USBIRQ or EPIRQ), and checks it using various bit masks to determine the source of the interrupt. For example, to test for the SUDAVIRQ interrupt request, firmware would read R11 (EPIRQ) and AND the result with 00100000 (the SUDAVIRQ bit is in the bit 5 position). Typically, a program will equate a label like bmSUDAV with 0010000. Once the IRQ bit is detected to be a 1, the firmware can simply write the mask value back to the register (SUDAVIRQ = bmSUDAV) and only the desired bit is cleared. IRQ bits written with a zero are unchanged.