Read bitfield s phyX_pkt_cnt, where X can be 0,1,2, or 3. These registers will appear to output random values while CSI data is being output. Note: Due to the random output, there will be a 1 in 256 chance…
Check the packet counter register on the deserializer for the data output. For example, check register 0x40 for the selected type Link A in the MAX96724 camera devices.
Ensure that number of lanes, lane…
Set VID_TX_EN = 0 for all pipes. In this condition, MIPI input can be enabled and MIPI error can be re-detected if it is there. Then when the module is allowed to transmit video, VID_TX_EN can be enabled…
Yes, the triggering mechanism should be identified and eradicated during the design time. There are cases that there is a good stream received by the video sink even though MIPI_ERR FLAG is asserted on…
Changin settings on many interfaces (CSI, eDP) will cause an interruption in the transmission of the video data (the device immediately halts). Most connected SoCs at a minimum will report this as a transmission…
There is not a definitive way to tell which line had the error. The interrupt is asynchronous with respect to the video output because it is generated at the video pipes, in the middle of the datapath…
Ensure that the serializer and deserializer are programmed correctly, check lane map, polarity, number of lanes, datatypes etc.
Make sure you have PCLKDET on serializer and video_lock on deserializer…
For a video pipe’s GMSL2 VID_LOCK signal to be asserted, the video pipe must continuously receive at least 16 valid video packets within a moving time window. A video pipe’s video packet detector counts…
