RoR mode gets enabled via serializer configuration (CFG) pins at power-up. It can also be enabled after power-up using register writes.
There is no configuration or modification required on the RoR capable…
GMSL serializers that support RoR mode operate precisely from the clock reference extracted from the reverse channel via a GMSL deserializer that supports RoR.
Note- Only certain GMSL serializers and…
The Deserializer uses the Frame Difference measurement (FRM_DIFF) which measures the difference between VSYNC signals, and the Overlap Window (OVLP_WINDOW) which measures the time from issuing an FSYNC…
Yes, as long as long as appropriate PHY interface is used and configured appropriately. FPGAs use a non-continuous clock so bitfield MIPI_NONCONTCLK_EN must be set appropriately.
RoR eliminates the external components of the oscillator circuitry required for the serializer; this results in reducing complexity, PCB area and cost.
Line aggregation of WxH is only supported on multiple input (e.g. quad) CSI-2 deserializers and only in pixel mode. For tunneling mode, or single input deserializers, use First Come First Serve aggregation…
By default, the Main Link is whichever link gets LOCKED first and is used as the reference for the internally generated frame synchronization modes. If desired, the user can explicitly define one link…
