| 12-bit monochrome video data includes 12 bits of data + HS+VS+DE = 15 parallel into a GMSL device like the MAX9275, per sample. So, BWS = 0 (24-bit mode) configuration allows a pixel clock frequency up to 104MHz. Any unused inputs will be internally pulled low and filled with zero (but scrambled and 8b/10b coding on the GMSL). It can be left open. The resolution would be 1412 x 1028 @54 FPS, hence the pixel clock would be 78,4MHz. With two CSI-2 lanes the data rate per lane would be 78,4 MHz x 15/2 = 588Mbps, meaning that there is no issue as seen in the table in the datasheet. |