The I2C/UART functions, whether control channel or pass through, are not affected by the speed group settings. The I2C/UART circuitry has a fixed falling-edge slew rate, and the rising-edge slew rate is…
There are blanking requirements stated in the data sheet, and zero blanking time is not supported.
In general, CVT-RB timings are a good place to start for video timing proposals, then modified as needed…
On Dual/Quad deserializers, when some of the links are in tunnel mode and others are in pixel mode, the limitation exists that users cannot aggregate tunnel and pixel mode data streams. Users may aggregate…
A single design can meet requirements for both GMSL1 and GMSL2 operation if some very simple rules are followed:
The system must meet the GMSL1 or GMSL2 channel specification.
The GMSL link AC-coupling…
Check the packet counter register on the deserializer for the data output. For example, check register 0x40 for the selected type Link A in the MAX96724 camera devices.
Ensure that number of lanes, lane…
The RoR mode does not affect the EMI/EMC radiated emissions or conducted emissions results. Clock information is embedded in data packets from the deserializer to the serializer. Since the packets are…
GMSL2 has both forward and reverse data. Due to the proprietary nature of the GMSL link, a customer will not be able to see meaningful data.
It is better to check for decode/PRBS/CRC errors.
Yes, as long as long as appropriate PHY interface is used and configured appropriately. FPGAs use a non-continuous clock so bitfield MIPI_NONCONTCLK_EN must be set appropriately.
Yes, but it requires programming the serializer and deserializer to match the MIPI interface lane configuration. GMSL2 devices can support 1, 2, 3, or 4-lane D-PHY configurations.
GMSL2
