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  • FAQ

    Which GMSL parts support line aggregation?

    Line aggregation of WxH is only supported on multiple input (e.g. quad) CSI-2 deserializers and only in pixel mode. For tunneling mode, or single input deserializers, use First Come First Serve aggregation.
  • FAQ

    How is Link Margin performed?

    Link margin testing is performed by reducing the peak-to-peak source voltage until an error has occurred.
  • FAQ

    What are the benefits of using the reference clock output function?

    The reference clock output enables efficient utilization of crystals or other frequency references. By utilizing the reference clock output, a single crystal can provide the frequency reference for multiple GMSL devices. In addition, the flexibility provided…
  • FAQ

    What reference clock output modes do GMSL devices provide?

    Depending on the device, three reference clock output modes that may be supported (a given device may not support reference clock output at all or it may support any or all of the modes): Fixed 25MHz output Integer divided 25MHz output (divide by…
  • FAQ

    How can the GMSL reference clock input be generated?

    The reference clock is most commonly generated by connecting a 25MHz crystal to the crystal oscillator pins of the GMSL device An external device, such as another GMSL device or TCXO, can alternatively provide the reference clock input