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LTC6957 - Help with buffer/level shifting

Hello,

I'm trying to figure out how to pass terminated trigger signal from an FPGA to a GaN FET driver (LMG1020).  The FPGA can produce a single ended 1.8V signal or a 1.8V LVDS signal (Xilinx documentation says this bank @1.8V can do LVDS) that will go to the LMG1020.  Because this signal will be terminated, the signal will only have a magnitude of 0.9V (for the single ended version) so I need a buffer/level shifter to drive the FET driver (LMG1020).  The V_IH (input high voltage) max threshold for the fet driver (LMG1020) says 2.6V so I believe I need to drive the FET driver input to 2.6V or higher.  

I have found an LTC (which is now ADI) part which looks like it might be able to do this.  The LTC6957 looks like it can receive the 0.9V input and convert it to an LVDS or CMOS output.

So, my questions are:

1. With a 50kHz or slower trigger could I use the LTC6957 to do this?  My trigger may range from single manual pulses (a few times a second or once a second) to 50kHz.  Is there a concern with using a signal this slow?  The part seems to be designed for clocks.

2.  Does it make sense to drive this with a single ended 1.8V terminated or would LVDS be better?

2a.  Should the trace from FPGA to LTC6957 be terminated with 50ohm or 100ohm or something different?

3. What exactly does the CMOS output mean?  

Any guidance would be helpful as this is somewhat unfamiliar territory for me.  I've attached a basic block diagram of what my architecture looks like.

Parents
  • Hello,

    You may want to also look at the LTC6752.  This comparator can accept LVDS or CMOS input.  Depending on which package option you select the CMOS output can range from 1.7V to 3.3V.  Its not as low phase noise as the LTC6957, but if you are interested you can ask if we have some phase noise (jitter) plots.  This circuit would not require the network shown below for the LTC6957.

    LTC6957

    The LTC6957-3/-4 both have a 3.3V CMOS output.  There is plot in the LTC6957 datasheet for the CMOS VOH/VOL vs load.  The LTC6957 accepts a DC coupled LVPECL input (see datasheet for recommended schematic), since its DC common mode is around 2V.   For other common LVDS (1.25V) or 1.8V CMOS (0.9V) inputs signals you will needed some sort of interface to DC couple into the LTC6957.   I've attached an LTSpice simulation of the below network.  This interface converts the LVDS common of 1.2V up closer to the desired 2V common of the LTC6957.  You may need to adjust the 130 ohm resistors value some in your simulations.  You can download LTSpice for free from the ADI website and simulate the attached file 'LTC6957 LVDS input.asc'.

  • Hi, looking for 'LTC6957 LVDS input.asc'. file as looks missing.

    Please a LTSPICE  (as I see only IBIS)  model for LTC6957 as CMOS, or LVPECL

    Hp

  • Hi,

    I've found the attached file on my computer.   Let see if this works. 

    LTSpice does not exist for the LTC6957.  In the datasheet there are plenty of interface schematics that have been fully tested and will work.  I would recommend copying those.  If you, are trying something different than the datasheet is proposing, let me know.  We can figure something out.

    Thanks

    Chris

    LTC6957 LVDS input.asc

  • Hi Chris,

    thank you, I expected a full model of the LTC6957 so I could simulate the full chain starting from any oscillator Grinning and use it as a dual clock distributor.

    BTW:

    - how this LTC6957 is sensitive to "Chatter" as required minimal rise time?

    - Are there any newer designs as any better in jitter terms as 3.3V CMOS from oscillator to CMOS / LVPCEL outputs

    Thank you Hp

  • There are some plots in the LTC6957 that compare output noise to sinewave input level.  You can compare those CMOS rise times to the sinewave rise time, equations below.  The LTC6955 is a good one, but it has CML outputs that should work with LVPECL input.  It is an 11 output, but can power up with only 3 outputs on.  The LTC6957 is pretty unique in terms of power dissipation, size and performance.

    You could add some hysterisis to the input by connecting the output via resistor to the input.  This would limit the chatter, but affects duty cycle. The LTC6752 (not 6957) datasheet figure 6 describes this technique more.  Something like this could be used on the 6957 possibly.

    What are you trying to simulate?  Functionality or phase noise performance?

    Chris

Reply
  • There are some plots in the LTC6957 that compare output noise to sinewave input level.  You can compare those CMOS rise times to the sinewave rise time, equations below.  The LTC6955 is a good one, but it has CML outputs that should work with LVPECL input.  It is an 11 output, but can power up with only 3 outputs on.  The LTC6957 is pretty unique in terms of power dissipation, size and performance.

    You could add some hysterisis to the input by connecting the output via resistor to the input.  This would limit the chatter, but affects duty cycle. The LTC6752 (not 6957) datasheet figure 6 describes this technique more.  Something like this could be used on the 6957 possibly.

    What are you trying to simulate?  Functionality or phase noise performance?

    Chris

Children
  • Hi Chris,

    what this GV/s compares as good or bad, while did not find any references.

    IMHO, PN using LTSpice is may impossible as trans is not accurate handled, as it shows on data export or wave files.

    Currently have a clock distributor witch allows sync clock on & off as the AKM ADC requires.

    >> What are you trying to simulate?

    just the full chain from crystal to clock distributor output.

    More details about the setup & gotchas in a PM.

    Hp

  • GV/s = giga volt per second.  The table provided an example of equations to convert sine waves to slew rate.  The LTC6957 datasheet has noise floor plots vs sinewave frequency and amplitude.  Using the equation with these plots should give you some idea of the minimum slew rate.  I'm not sure if you are trying to hit a certain phase noise floor target or see where it stops functioning correctly.

  • Well, soon back on lab will measure existing OXCO's and than feed the LTC6957 as a clock distributor and will test once more as flicker or chatter O;) as results discussed preferred by PM...