LTC6957 - Help with buffer/level shifting

Hello,

I'm trying to figure out how to pass terminated trigger signal from an FPGA to a GaN FET driver (LMG1020).  The FPGA can produce a single ended 1.8V signal or a 1.8V LVDS signal (Xilinx documentation says this bank @1.8V can do LVDS) that will go to the LMG1020.  Because this signal will be terminated, the signal will only have a magnitude of 0.9V (for the single ended version) so I need a buffer/level shifter to drive the FET driver (LMG1020).  The V_IH (input high voltage) max threshold for the fet driver (LMG1020) says 2.6V so I believe I need to drive the FET driver input to 2.6V or higher.  

I have found an LTC (which is now ADI) part which looks like it might be able to do this.  The LTC6957 looks like it can receive the 0.9V input and convert it to an LVDS or CMOS output.

So, my questions are:

1. With a 50kHz or slower trigger could I use the LTC6957 to do this?  My trigger may range from single manual pulses (a few times a second or once a second) to 50kHz.  Is there a concern with using a signal this slow?  The part seems to be designed for clocks.

2.  Does it make sense to drive this with a single ended 1.8V terminated or would LVDS be better?

2a.  Should the trace from FPGA to LTC6957 be terminated with 50ohm or 100ohm or something different?

3. What exactly does the CMOS output mean?  

Any guidance would be helpful as this is somewhat unfamiliar territory for me.  I've attached a basic block diagram of what my architecture looks like.

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  • 0
    •  Analog Employees 
    on Aug 16, 2018 11:23 PM over 2 years ago

    It's not an exact 50 ohm match, but the reflections are far enough away from the hysteresis point, that you should be ok.  We built this circuit for a different device a couple years ago, so I had to go back to the original simulation tool with the transmission lines.  Below are the results of the above circuit with a 3 inch transmission line using a pulse.   We also simulated this with different length transmission lines, the voltage levels for the reflections will stay the same, but they maybe wider or shorter (in time) depending on the length of the transmission line.  You will need a cable ( & SMA) for each LVDS leg.  Also this circuit assumes a true LVDS output (constant current).  If the FPGA vendor has made their output LVDS-like in terms of voltage levels (but not a current based output), then we may need to come up with something else.   If any of this causes concern, the LTC6752 is another option (see comment in first response). 

    True LVDS  (https://en.wikipedia.org/wiki/Low-voltage_differential_signaling)

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  • 0
    •  Analog Employees 
    on Aug 16, 2018 11:23 PM over 2 years ago

    It's not an exact 50 ohm match, but the reflections are far enough away from the hysteresis point, that you should be ok.  We built this circuit for a different device a couple years ago, so I had to go back to the original simulation tool with the transmission lines.  Below are the results of the above circuit with a 3 inch transmission line using a pulse.   We also simulated this with different length transmission lines, the voltage levels for the reflections will stay the same, but they maybe wider or shorter (in time) depending on the length of the transmission line.  You will need a cable ( & SMA) for each LVDS leg.  Also this circuit assumes a true LVDS output (constant current).  If the FPGA vendor has made their output LVDS-like in terms of voltage levels (but not a current based output), then we may need to come up with something else.   If any of this causes concern, the LTC6752 is another option (see comment in first response). 

    True LVDS  (https://en.wikipedia.org/wiki/Low-voltage_differential_signaling)

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