I'm trying to figure out how to pass terminated trigger signal from an FPGA to a GaN FET driver (LMG1020). The FPGA can produce a single ended 1.8V signal or a 1.8V LVDS signal (Xilinx documentation says this bank @1.8V can do LVDS) that will go to the LMG1020. Because this signal will be terminated, the signal will only have a magnitude of 0.9V (for the single ended version) so I need a buffer/level shifter to drive the FET driver (LMG1020). The V_IH (input high voltage) max threshold for the fet driver (LMG1020) says 2.6V so I believe I need to drive the FET driver input to 2.6V or higher.
I have found an LTC (which is now ADI) part which looks like it might be able to do this. The LTC6957 looks like it can receive the 0.9V input and convert it to an LVDS or CMOS output.
So, my questions are:
1. With a 50kHz or slower trigger could I use the LTC6957 to do this? My trigger may range from single manual pulses (a few times a second or once a second) to 50kHz. Is there a concern with using a signal this slow? The part seems to be designed for clocks.
2. Does it make sense to drive this with a single ended 1.8V terminated or would LVDS be better?
2a. Should the trace from FPGA to LTC6957 be terminated with 50ohm or 100ohm or something different?
3. What exactly does the CMOS output mean?
Any guidance would be helpful as this is somewhat unfamiliar territory for me. I've attached a basic block diagram of what my architecture looks like.
I believe the signal standards for LVDS2_5 and LVDS1_8 for Xilinx IO both meet the LVDS signal standard and expect them to be able to drive the link appropriately. I know the IO is capable of driving…
Unfortunately we don't have additive phase jitter specified for ADN4662.
I'm not familiar with LTC6957, so I'll check if someone else can provide some inputs on that.