I'm trying to figure out how to pass terminated trigger signal from an FPGA to a GaN FET driver (LMG1020). The FPGA can produce a single ended 1.8V signal or a 1.8V LVDS signal (Xilinx documentation says this bank @1.8V can do LVDS) that will go to the LMG1020. Because this signal will be terminated, the signal will only have a magnitude of 0.9V (for the single ended version) so I need a buffer/level shifter to drive the FET driver (LMG1020). The V_IH (input high voltage) max threshold for the fet driver (LMG1020) says 2.6V so I believe I need to drive the FET driver input to 2.6V or higher.
I have found an LTC (which is now ADI) part which looks like it might be able to do this. The LTC6957 looks like it can receive the 0.9V input and convert it to an LVDS or CMOS output.
So, my questions are:
1. With a 50kHz or slower trigger could I use the LTC6957 to do this? My trigger may range from single manual pulses (a few times a second or once a second) to 50kHz. Is there a concern with using a signal this slow? The part seems to be designed for clocks.
2. Does it make sense to drive this with a single ended 1.8V terminated or would LVDS be better?
2a. Should the trace from FPGA to LTC6957 be terminated with 50ohm or 100ohm or something different?
3. What exactly does the CMOS output mean?
Any guidance would be helpful as this is somewhat unfamiliar territory for me. I've attached a basic block diagram of what my architecture looks like.
I believe the signal standards for LVDS2_5 and LVDS1_8 for Xilinx IO both meet the LVDS signal standard and expect them to be able to drive the link appropriately. I know the IO is capable of driving…
If you provide a terminated LVDS output from the FPGA, then ADN4662 (single LVDS receiver) could be used to convert to a single-ended signal to interface to LMG1020. Output high from ADN4662 is a minimum of 2.7V.
Some discrete level shifting circuit might be possible too, especially with the data rate as low as 50 kHz. The LVDS option is simply handy if you want to stick to regular operating modes for both FPGA output and LMG1020 input and make sure everything just works as expected.
For the ADN4662, where in the data sheet can I find the phase jitter? I'm trying to use a part that induces minimum error while passing this trigger signal through it. We need to characterize the propagation delay through our signal chain as accurately as possible. This is why I was originally looking at the LTC6957. Where do I find the number describing the amount of error the ADN4662 will induce from this perspective?
Also, what would be the benefit of using the ADN4662 over the LTC6957?
Unfortunately we don't have additive phase jitter specified for ADN4662.
I'm not familiar with LTC6957, so I'll check if someone else can provide some inputs on that.
You may want to also look at the LTC6752. This comparator can accept LVDS or CMOS input. Depending on which package option you select the CMOS output can range from 1.7V to 3.3V. Its not as low phase noise as the LTC6957, but if you are interested you can ask if we have some phase noise (jitter) plots. This circuit would not require the network shown below for the LTC6957.
The LTC6957-3/-4 both have a 3.3V CMOS output. There is plot in the LTC6957 datasheet for the CMOS VOH/VOL vs load. The LTC6957 accepts a DC coupled LVPECL input (see datasheet for recommended schematic), since its DC common mode is around 2V. For other common LVDS (1.25V) or 1.8V CMOS (0.9V) inputs signals you will needed some sort of interface to DC couple into the LTC6957. I've attached an LTSpice simulation of the below network. This interface converts the LVDS common of 1.2V up closer to the desired 2V common of the LTC6957. You may need to adjust the 130 ohm resistors value some in your simulations. You can download LTSpice for free from the ADI website and simulate the attached file 'LTC6957 LVDS input.asc'.
Thank you very much for this! This is very helpful!
1. I've got the sim running and I see LVDS toggling from 1.0V to 1.4V around a Vcm of 1.2V. I will be using 1.8V LVDS from a high performance FPGA IO bank (hard limit is 1.8V) so is it correct to expect this to have a common mode voltage of 0.9V as you mentioned and therefore design the termination network to take a 0.9V +/- 100mV and convert it to LVPECL?
2. For LVPCL - you mentioned that the Vcm should be around 2V. I see in the sim that it is around 1.85V. Is this ok or is this where the 130R resistor adjustment comes in?
3. For LVPECL - do I just have to make sure the VCM and Vdiff levels are hit? I don't have to worry about current/load driving characteristics? It seems like this termination network could be a good solution if I just have to hit the correct voltage levels.
4. Do R21 and R2 represent the transmission line?
5. Should pulldowns R4 and R3 be placed at the source? In this case as close to my FPGA balls as possible?
6. Will this termination induce ringing and reflections due to the pull-downs (R3, R4) and pull-ups (R1, R13) at either end?
7. I have to connect this FPGA PCB trigger signal to a diode driver PCB so I will have to have some sort of cable harness. Can you preserve signal integrity with a wiring harness? I'm unsure if LVDS will work (it seems like the ideal case), but could I be forced to a 50 ohm single ended signal/cable to get a good transmission line?
Thanks again for all your help!