Understanding pulse width distortion and minimum pulse width requirement

Hello

We would like to use the ADuM262N to transmit a clock signal of 85MHz or even 100MHz. This could cause problems with the given maximum PWD of 5ns. We made some quick test and the PWD was <1ns in the temperature range that is of interest to us. Thus, my question is, under what circumstances can the PWD become >2ns or achieve the maximum 5ns?


Best regards
Hans

Parents
  • +1
    •  Analog Employees 
    on Feb 5, 2018 6:03 PM

    Hans,

    You might also consider the ADN465x family. The maximum pulse skew is 100 ps on a given channel, and 300 ps channel to channel for the ADN4650 (500 ps for the ADN4651/52). There is a power trade-off since this family is designed to operate at much higher throughput of 600 Mbps with extremely low delay and jitter.

    DaveC

Reply
  • +1
    •  Analog Employees 
    on Feb 5, 2018 6:03 PM

    Hans,

    You might also consider the ADN465x family. The maximum pulse skew is 100 ps on a given channel, and 300 ps channel to channel for the ADN4650 (500 ps for the ADN4651/52). There is a power trade-off since this family is designed to operate at much higher throughput of 600 Mbps with extremely low delay and jitter.

    DaveC

Children
No Data