We would like to use the ADuM262N to transmit a clock signal of 85MHz or even 100MHz. This could cause problems with the given maximum PWD of 5ns. We made some quick test and the PWD was <1ns in the temperature range that is of interest to us. Thus, my question is, under what circumstances can the PWD become >2ns or achieve the maximum 5ns?
Best regards Hans
Thank you for your reply. You mentioned that you collected a lot of data regarding supply voltage/working temp/different channels. That's exactly what interests me, is the maximum pwd just a cornercase that can occur e.g. at highest temperature, lowest supply voltage and low impedance load in a certain percentage of chips?
First I thought that possibly the max pwd could be ruled out since we only plan to use the isolator between 20°C - 60°C, (feeding a high-impedance load). At least that was the case with the isolator from an other company that we are currently using. Its pwd strongly increases with temperature. I'm not sure whether this is the case for the ADuM262N. According to the datasheet, the typical change in temperature is only 1.5ps/°C but on the other hand, the typical pwd is also only 0.7ns.
If you do have any data for a reduced temperature range of e.g. 20°C - 60°C, I would really appreciate it. Most interesting would be max( t_plh - t_phl ) and min( t_phl - t_plh ). If the pwd is for example always positive, we could apply duty cycle correction.