Understanding pulse width distortion and minimum pulse width requirement

Hello

We would like to use the ADuM262N to transmit a clock signal of 85MHz or even 100MHz. This could cause problems with the given maximum PWD of 5ns. We made some quick test and the PWD was <1ns in the temperature range that is of interest to us. Thus, my question is, under what circumstances can the PWD become >2ns or achieve the maximum 5ns?


Best regards
Hans

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    •  Analog Employees 
    on Jan 29, 2018 12:14 AM

    Hello Hans,

    Glad to hear that you are interested in our six channel OOK part. To be honest, the part has a guaranteed maximum 150 Mbps data rate, so for your clock signal above 75 MHz, the performance would be different from what we have in the datasheet. You mentioned that you had a quick test on the chip and the PWD was <1ns, and you should know that there would have chip to chip variations, the maximum PWD value is collected from lots of testing results in terms of supply voltage/working temp/different channels.

    Regards,

    Neil

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  • 0
    •  Analog Employees 
    on Jan 29, 2018 12:14 AM

    Hello Hans,

    Glad to hear that you are interested in our six channel OOK part. To be honest, the part has a guaranteed maximum 150 Mbps data rate, so for your clock signal above 75 MHz, the performance would be different from what we have in the datasheet. You mentioned that you had a quick test on the chip and the PWD was <1ns, and you should know that there would have chip to chip variations, the maximum PWD value is collected from lots of testing results in terms of supply voltage/working temp/different channels.

    Regards,

    Neil

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