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Understanding pulse width distortion and minimum pulse width requirement


We would like to use the ADuM262N to transmit a clock signal of 85MHz or even 100MHz. This could cause problems with the given maximum PWD of 5ns. We made some quick test and the PWD was <1ns in the temperature range that is of interest to us. Thus, my question is, under what circumstances can the PWD become >2ns or achieve the maximum 5ns?

Best regards

  • Hello Hans,

    Glad to hear that you are interested in our six channel OOK part. To be honest, the part has a guaranteed maximum 150 Mbps data rate, so for your clock signal above 75 MHz, the performance would be different from what we have in the datasheet. You mentioned that you had a quick test on the chip and the PWD was <1ns, and you should know that there would have chip to chip variations, the maximum PWD value is collected from lots of testing results in terms of supply voltage/working temp/different channels.



  • Hello Neil

    Thank you for your reply. You mentioned that you collected a lot of data regarding supply voltage/working temp/different channels. That's exactly what interests me, is the maximum pwd just a cornercase that can occur e.g. at highest temperature, lowest supply voltage and low impedance load in a certain percentage of chips?

    First I thought that possibly the max pwd could be ruled out since we only plan to use the isolator between 20°C - 60°C, (feeding a high-impedance load). At least that was the case with the isolator from an other company that we are currently using. Its pwd strongly increases with temperature. I'm not sure whether this is the case for the ADuM262N. According to the datasheet, the typical change in temperature is only 1.5ps/°C but on the other hand, the typical pwd is also only 0.7ns.

    If you do have any data for a reduced temperature range of e.g. 20°C - 60°C, I would really appreciate it. Most interesting would be max( t_plh - t_phl ) and min( t_phl - t_plh ). If the pwd is for example always positive, we could apply duty cycle correction.

    Best regards


  • Hi Hans,

    I checked with our test engineer that we collect the data at 25C and the temperature extremes(-40C and 125C), and we do not have any data on the reduced temperature range of 20C to 60C. The PWD distortion can be either a positive or negative number, so a duty cycle correction would not necessarily compensate for the PWD.



  • Hans,

    You might also consider the ADN465x family. The maximum pulse skew is 100 ps on a given channel, and 300 ps channel to channel for the ADN4650 (500 ps for the ADN4651/52). There is a power trade-off since this family is designed to operate at much higher throughput of 600 Mbps with extremely low delay and jitter.