ADUM5402

Kabasakal-san:

What is your SPI clock speed?  It is important in SPI applications to look at the maximum prop delay and the clock speed.   In SPI applications, the clock pulse rising and falling edge will clock the data out and back through the digital isolator channels, which will make the overall delay greater than 4 times the prop delay.  When the part is hot the prop delay may be at the max, and for the ADuM5402A, the max prop delay is 100ns times 4 is 400ns, so the max clock frequency would be 1/400ns = 2.5MHz.

You may get different prop delay for different lots numbers of the ADuM5402A, but the design should be to be able to use the max prop delay to allow for different lots as there will be process variations.  

Another option may be to try the ADuM5402C, which has a max prop delay of 60ns.

Regards, Brian

Hi,

Firstly, thanks for your answer. My clock frequency is 67KHz. It is not even close to the 2.5MHz. The design is working for more than 10 years but in some boards I got this problem. What do you mean by ADUM5402A or ADUM5402C? Is it ADUM5402ARWZ and ADUM5402CRWZ or the revisions ? 

Thanks.

Kabasakal:

67kHz is a very slow clock - what is the pulse width of the clock pulse? Can you send me a waveform of the clock and data in and out when you see the problem and the amount of shift of your SPI data?

Regards, Brian

Kabasakal-san:

In answer to your question, by the ADUM5402A I mean the ADUM5402ARWZ which has 100ns max prop delay. By the ADUM5402C I mean the  ADUM5402CRWZ which has a max of 60ns prop delay.

I await your answer to my request.

Regards, Brian

The waveform is like this;

I will try to use CRWZ instead of ARWZ as you adviced. When the board heated, the coming data is started to shift as I mentioned but I'm not sure when the shifting starts. As a decimal I should see a result as 6 (............0110) but I see 27(.........11110).

Thanks.