ADuM6401 output state at VDD1 off

Hello

Please let me know your adivce for  output state of ADUM6401 at VDD1 off.

We think  that output becomes high-impedance throguh below 2 pattern  from the datasheet description.

Is it correct ?

1:   ADuM6401 holds last logic state

2:   output becomes high -impedance when VISO reaches UVLO

Or

1: ADuM6401 holds last logic state

2: output is set to default low  temporarily because there is not  input data pulse

3:  output becomes high -impedance when VISO reaches UVLO

Regards,

Terumasa

Parents
  • Hello Brian,

    Thank you for your answer.

    Application is measurement equipment and ADUM6401 is used for the communication and power supply to external controller.

    When any toruble is appeared , VDD1 may be turn-off.

     So, we would like to know  wheter output at VDD1-off is high-impedance or low or indeterminate.

    The datasheet says below and I thought that Output state finally turn High-Impedance.

    "

    Either the UVLO level is reached and the outputs are placed in their high impedance state, or the outputs detect a lack of activity from the primary side inputs and the outputs are set to their default low value before the secondary power reaches UVLO."

    My understanding from your answer is below  and is it correct ?

    Output is indetermiante before VDD1 reaches UVLO  ( VDD1 ~ 2.6V and so on) ,

    output is low when VDD1 reaches UVLO   and  Output  is  high impedance at VDD1-off .

    Regards,

    Terumasa

Reply
  • Hello Brian,

    Thank you for your answer.

    Application is measurement equipment and ADUM6401 is used for the communication and power supply to external controller.

    When any toruble is appeared , VDD1 may be turn-off.

     So, we would like to know  wheter output at VDD1-off is high-impedance or low or indeterminate.

    The datasheet says below and I thought that Output state finally turn High-Impedance.

    "

    Either the UVLO level is reached and the outputs are placed in their high impedance state, or the outputs detect a lack of activity from the primary side inputs and the outputs are set to their default low value before the secondary power reaches UVLO."

    My understanding from your answer is below  and is it correct ?

    Output is indetermiante before VDD1 reaches UVLO  ( VDD1 ~ 2.6V and so on) ,

    output is low when VDD1 reaches UVLO   and  Output  is  high impedance at VDD1-off .

    Regards,

    Terumasa

Children
No Data