Adum4136 Damage with Ready pin low


I am using the Adum4136 to drive IGBTs in DC-AC converter. The circuits have worked well but I am suffering occassionally damage of Adum4136. When it goes wrong, the fault pin keeps high and the ready pin keeps low. Some of them are damaged when the power circuits are not powered up. At least 4 of them are damaged when I was re-programming the FPGA and my fault detection circuit indicated something went wrong. Reset the circuits cannot fix it but it  can be fixed by repalce the Adum4136 with a new one.  Is it possible to find out a way to avoid this?

I am using isolated DC/DC supply to generate 15V and -9V for the high voltage side. Desat pin is connected to 100pf capacitor and 1K resistor to the C terminal of IGBT. 12 Adum4136 are sharing the low voltage side 5V supply. Their ready and fault pin are pulled up by 10K resistor and Ready pins are connected together to achieve wired AND thanks to the OC gate designed for this pin.So are the Fault pins. The 47 ohm gate reistors are used to avoid exceeding the 4A output capacity. The Ready and Fault pin are connected to a AND gate (SN74HC20).

  • Hi RSchnell,

    Thanks for your reply.

    Answers are as follows:

    Q1) When it is damaged, the output does not work. Although my design dosesn't allow it to work with ready pin or fault pin low, I can still say it is not working as the DC/DC module for the secondary side went very hot. I was using a programmable power supply with current limiting function for the gate drivers, so the DC/DC modules survived.

    Q2) I was not able to measure the current for the single damaged gate driver. But with the help of the programmable power supply for the control circuits, the current went higher than normal condition (0.8A), reaching the limited value (1.5A) I set. 

    Q3) Yes it worked for a while. I am not sure if ESD can be the reason but I guess it is possible. Our soldering station is gounded but it is very dry here in northern Canada. So static electricity is easy to generate. But I didn't find any noticable ESD while soldering.

    BTW, I am ok with the slow rising edge as we are operating the prototype in low switching frequency, but good to know the potential of this IC. Thanks a lot.

  • Thanks RSchnell,

    I guess violations on VDD2 might be the reason. I just measured the resistance between VSS and VDD of the removed IC, showing 112 ohm. Comparing to a funcitonal one, the resistance is more than 100K ohm. But the resistance between Vss and GND2 is still infinity, so is the resitance between VDD and GND2. 

    Adding a TVS between VSS and VDD might be a solution.  But I am still wondering how could the overvoltage be generated? The dc/dc module?

    Do you have any futher suggestions? 

  • 0
    •  Analog Employees 
    on Nov 21, 2017 3:31 AM


    Your circuit schematic looks good, and I cannot see any problems with it.

    The ready and fault signals go from the secondary side to the primary side of the IC using a single internal communication coil. The encoding is such that for a fault to register, a ready signal would be present. Without looking at waveforms, or having the part in front of me, the possible things that could be going wrong are:

    1) The back communication channel could be damaged.

       a) The only thing that I can think that could do this is an abs max violation on VDD2 to VSS2. This could either be above or below the abs max limits. I would expect the output channel to not work if this is the case.

    2) The open-drain outputs are being damaged somehow

       a) This could be from negative voltage being applied to nFault or Ready relative to GND1. This would require a lot of sustained current, so I don't think this is the cause as you have a large pull-up resistor that will limit any attempt at current going through the body diode.

    Q1) When the parts are damaged, does the output still work? Is it as if the part is functioning correctly, but just not reporting READY or nFault?

    READY will be low if the secondary side is not powered up, or if the secondary side thermal shutdown (TSD) activates. The IC would be too hot to touch if the TSD is triggering.

    Q2) When the secondary side is powered up, but the READY signal is low, what is the quiescent current going into the ADuM4136 secondary side (VDD2 to VSS2) when not switching?

    Q3) Do the parts work for a while, then not work, or are you finding parts that are damaged as soon as they are soldered on the board? Could ESD be a possibility for the damage?

    One note about the 4 A number. 4 A is the target peak current in application for the ADuM4136, but the actual saturation current of the output drives is much higher, in the 8 A or higher range. Figure 21 in the datasheet shows some possible output currents achievable on the part. With a 47 Ω resistor, you are getting less than 0.5 A peak current right now, and if you want a faster rise time, you can definitely reduce this value. If you are happy with the rise times right now, a larger resistor helps dissipate more of the power outside of the gate driver, so a larger external series gate resistor is better for thermal performance.


  • 0
    •  Analog Employees 
    on Nov 21, 2017 4:05 AM


    It is sounding like the secondary side is getting damaged. Is there any chance the VDD2 is seeing a negative voltage or voltage above 40 V referenced to the VSS2 pin?

    This is sounding less like ESD, and more like some transient is affecting the IC. Things I would look for are:

    1) abs. max violations on VDD2

    2) negative voltage on the DESAT pin (sometimes seen during high current operations in other reported applications from other people.


  • 0
    •  Analog Employees 
    on Nov 21, 2017 5:56 AM

    A TVS diode could be an option. If you have an isolated voltage probe, you might be able to see the turn on transient of the DC/DC converter on startup. It might show a spike. A TVS diode would probably suppress that if it does exist. It's too early to pin the blame on the DC/DC converter. The ADuM4136 abs. max rating is 40 V, but it would probably take a much larger than 40 V spike to hurt it. To be safe though, operation must always be less than 40 V on VDD2 to VSS2.