ADUM5401 and ADM3053: Question Regarding Board Layout to Reduce EMI

Background:

  • We are using 3 ADUM5401 (RS485 serial) and 1 ADM3053 (CAN bus) to isolate 4 communication ports on a very compact (roughly 8 cm square) 4 layer circuit board with a DSP.
  • We are currently having trouble complying with the radiated EMI requirements of EN60945 when cables are connected to the communication ports. However, when the communication port cables are disconnected, we are well below the emission limits.  At this point I am not sure if this is related to lower current on the IsoPower circuits or because of the shielding effect of our enclosure or both.  Our biggest problems are at 358 MHz and 1073 MHz.  We are able to reduce the noise radiated from the cables by 4-8dBuV/m but only by using an unacceptably large number of high frequency and broadband ferrites.

I am now working on a re-layout of this circuit board to correct the issues.  I have read AN-0971 and AN-1349 and have the following questions:

In regard to Figure 1 in AN-1349 and its applicability to the ADM3053:

  • Assuming you have larger power and (“stitched”) ground planes in the circuit board layers below what is shown in this diagram, where should your vias be placed relative the capacitor and ferrite filtering components? Should they be right at the chip pins or should they be further away after the capacitors and ferrites in order to introduce a small amount of series inductance / resistance in some or all of these connections?
  • Can you please clarify or explain why most of the document examples show large power and ground planes extending out of the stitching overlap area and yet there is one line on page 3 of AN-1394 that says “To allow additional margin for passing emission limits, the GND2 plane area must be minimized.” So other than the stitching overlap zone, should we even have a GND2 plane?  Also please confirm that there should also be no positive power plane on the isolated side.

In regard to the ADUM5401 and AN-0917:

  • Again, where should vias to the power and ground plans be placed in relation to the filter capacitors?
  • Can the discrete stitching capacitor still be placed as close as possible to pins 8 and 9?
  • With the ADUM5401 should we still try to keep the isolated power and ground planes as small as possible outside the stitching area as described in AN-1349?

In regards to preventing the noise from leaving the circuit board on the signal lines which connect via plug in connectors and seem to act as antennas externally:

  • Do you have any experience or recommendations of the most effective ways to prevent this with these IsoPower circuits? 
  • Obviously feed through capacitors with the capacitor connected to our enclosure shield ground is the traditional method to deal with this but it would be useful to have further information on how this works in the real world with these Isopower chips and with signal lines connected to the isolated side of these circuits.
  • Any suggestions on the best parts and configuration to use for this application would be greatly appreciated.
Parents
  • Hello b_rad,

    Thank you for contacting us here in engineering zone.

    As you discussed there may be two different influences here for the larger emissions with the cable attached. How much pass margin do you require on EN60945?

    1. The cable may be loading the RS485 and CAN devices and hence drawing more current from the isoPower devices hence increasing the emissions.

    2. The cable may be acting like an antenna and providing an efficient antenna for the 360 MHz harmonic.

    Can you provide any information on the cable you are using? Is there resistive loads (120 Ohms or other) on the RS485/CAN bus output pins? What data rates are you operating at? These parameters will help determine the expected emissions. Is the PCB in a metal enclosure? Please contact me directly at james.scanlon@analog.com if you wish.

    To answer your questions in relation to AN-1349 and its applicability to the ADM3053E:

    1. If it is vias for the stitching cap the vias should be placed as close as possible to PIN 11 and to PIN 14. The GND2 (isolated) layer and the VISOUT out layer (secondary side PCB layers) should not be connected to Pins 11/14/12. These pins should only be connected to the secondary side PCB layers through the ferrite beads as shown in figure 1 in AN-1349. This is also shown in figure 18. For each of the isoPower devices do you have a separate stitching capacitor or one full stitching capacitor the length of the board that all devices are connected to?

    2. In order to achieve better emission data it is best to have minimum copper on the secondary side. However this is not always possible as many designs require planes for additional circuitry on the secondary side. The reference boards in that application note have secondary planes as this is often required. It is recommended tho for better results to remove as much copper (planes) as possible for better results.

    To answer your questions to the ADuM5401 and AN-0971:

    1. As described above the vias for the planes should be on the opposite side of the Ferrites to the ADuM5401. Again for this device pins 9 and 15 should only be connected to the secondary side GND2 plane through a Ferrite. Pins 9 and 15 on the ADuM5401 can be connected together similar to pins 14 and 11 on the ADM3053. Pin 16 on the ADuM5401 should only be connected though a ferrite to the VISO Plane. Also connect Vsel to either VISO or GNDiso on the ADuM5410 side of the ferrites.

    2. Yes the discrete capacitor should be placed as close as possible to pins 8 and 9. are you also using a stitching capacitor here?

    3. Yes better results are achieved with minimal copper on the secondary (isolated) side.

    By following the applications notes mentioned and by implementing the points above the with the proper selection of ferrites this should limit the 360 and 1G signals from the isolated planes and hence reduce the emissions when the cable is attached. What ferrites are you using? The stitching  and high voltage capacitor should provide a low impedance return path for the 360 CM noise. Please also refer to user guide UG-044 pages 4 and 5 for layout recommendations for the stitching capacitor and ferrite placement and PCB cutouts. 

    If you would like to provide images of your previous design/layout and your new design and layout I can review it to ensure all recommended layout guidelines are present.

    Can you provide and image of your test set-up. Is the issue horizontal or vertical emissions?

    Please contact me directly with any further questions and responses if you prefer. 

    Regards,

    James

Reply
  • Hello b_rad,

    Thank you for contacting us here in engineering zone.

    As you discussed there may be two different influences here for the larger emissions with the cable attached. How much pass margin do you require on EN60945?

    1. The cable may be loading the RS485 and CAN devices and hence drawing more current from the isoPower devices hence increasing the emissions.

    2. The cable may be acting like an antenna and providing an efficient antenna for the 360 MHz harmonic.

    Can you provide any information on the cable you are using? Is there resistive loads (120 Ohms or other) on the RS485/CAN bus output pins? What data rates are you operating at? These parameters will help determine the expected emissions. Is the PCB in a metal enclosure? Please contact me directly at james.scanlon@analog.com if you wish.

    To answer your questions in relation to AN-1349 and its applicability to the ADM3053E:

    1. If it is vias for the stitching cap the vias should be placed as close as possible to PIN 11 and to PIN 14. The GND2 (isolated) layer and the VISOUT out layer (secondary side PCB layers) should not be connected to Pins 11/14/12. These pins should only be connected to the secondary side PCB layers through the ferrite beads as shown in figure 1 in AN-1349. This is also shown in figure 18. For each of the isoPower devices do you have a separate stitching capacitor or one full stitching capacitor the length of the board that all devices are connected to?

    2. In order to achieve better emission data it is best to have minimum copper on the secondary side. However this is not always possible as many designs require planes for additional circuitry on the secondary side. The reference boards in that application note have secondary planes as this is often required. It is recommended tho for better results to remove as much copper (planes) as possible for better results.

    To answer your questions to the ADuM5401 and AN-0971:

    1. As described above the vias for the planes should be on the opposite side of the Ferrites to the ADuM5401. Again for this device pins 9 and 15 should only be connected to the secondary side GND2 plane through a Ferrite. Pins 9 and 15 on the ADuM5401 can be connected together similar to pins 14 and 11 on the ADM3053. Pin 16 on the ADuM5401 should only be connected though a ferrite to the VISO Plane. Also connect Vsel to either VISO or GNDiso on the ADuM5410 side of the ferrites.

    2. Yes the discrete capacitor should be placed as close as possible to pins 8 and 9. are you also using a stitching capacitor here?

    3. Yes better results are achieved with minimal copper on the secondary (isolated) side.

    By following the applications notes mentioned and by implementing the points above the with the proper selection of ferrites this should limit the 360 and 1G signals from the isolated planes and hence reduce the emissions when the cable is attached. What ferrites are you using? The stitching  and high voltage capacitor should provide a low impedance return path for the 360 CM noise. Please also refer to user guide UG-044 pages 4 and 5 for layout recommendations for the stitching capacitor and ferrite placement and PCB cutouts. 

    If you would like to provide images of your previous design/layout and your new design and layout I can review it to ensure all recommended layout guidelines are present.

    Can you provide and image of your test set-up. Is the issue horizontal or vertical emissions?

    Please contact me directly with any further questions and responses if you prefer. 

    Regards,

    James

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