Please see customer circuit attached:
SP_3_3V is UP before 3.3VA.
During this time NW_ISO_56N_PS1_OFFLINE_FPGA (pin 6) is driven High (which in turn switches OFF main power supply controlled through NW_ISO_56N_PS1_OFFLINE_FPGA signal) .
This is undesirable. So they shorted pins 6 and 7. This solves the problem. But due to this, the changes on pin 11 are not reflected on pin 6.
Basically, They are looking at option/solution to insure pin 6 remains low or High Z where +3.3VA is not up. +3.3VA is up after 1-2 seconds after SP_3_3V.