Please see customer circuit attached:

SP_3_3V is UP before 3.3VA.

During this time NW_ISO_56N_PS1_OFFLINE_FPGA (pin 6) is driven High (which in turn switches OFF main power supply controlled through NW_ISO_56N_PS1_OFFLINE_FPGA signal) .

This is undesirable. So they shorted pins 6 and 7. This solves the problem. But due to this, the changes on pin 11 are not reflected on pin 6.

Basically, They are looking at option/solution to insure pin 6 remains low or High Z where +3.3VA is not up.  +3.3VA is up after 1-2 seconds after SP_3_3V.


  • 0
    •  Analog Employees 
    on Jan 17, 2017 7:20 PM

    Hi yka,

    Please see the functional block diagrams and truth table of ADuM1401 below, Pin.7 is the output enable pin of VOD.

    This part has default high output when VDDI is unpowered and VDDO is powered.(From Table.15) 

    If customer shorted pin6&7 when SP_3_3V  is up and +3.3VA is not, I think the output should be high after SP_3_3V  is up, and I don't understand why they solved the problem, could you ask them to provide some pics of pin6&7 during the power up of  SP_3_3V?

    and when +3.3VA is powered up, if the input of VID is low, then the VE1 should be low and sets VOD to a "Z" state rather logic low state.

    There are two methods we can suggest:

    1. Using a signal to control VE1 pin, VE1 should be low until +3.3VA is powered up.

    2. Try our new OOK part, ADuM141E0 is pin compatible with ADuM1401 and has default low output.




  • 0
    •  Analog Employees 
    on Jan 20, 2017 5:15 AM

    Thanks for the prompt response and suggesting the alternative. As a work around the customer had shorted pins 7 and 8 not 6 and 7(He has a typo). But for the final application, he may consider what you have suggested. However he wondering if the followings are good crosses to either the ADUM1401AWRZ and ADUM141E0:


    SI Labs: Si8641BD-B-IS

    TI: ISO7641FCDWR

    They normally like to design in parts that have second source.