To Whom it May Concern,
In regards to the ADuM7442S Digital Isolator. Is there a guaranteed state at the outputs at Power On?
The scenario is that the Input Side is powered, and the Output Side just becomes powered (the Power On Event), are the Outputs of the device guaranteed to go from the tri-state "Z" State to the Input's State without ever taking on the opposite state of the Input's State? I.E. A Power On glitch to the opposite state.
I hope that is clear .
Regards
Hi,
Please see Table 19 in the datasheet, when VDDi is powered and VDDo is unpowered, the output should be in high impedance state, and "Outputs return to input input state within 1us of VDDo power restoration" as you can see.
To be honest, we could not guarantee whether the output state is when VDDo(powered) is under UVLO voltage, the state is uncertain. After the UVLO, 1us(max.) is needed to return to input state.
An application note listed below might be helpful:
Regards,
Neil
