Hi,
I got a problem with some ADuM4135s. I'm using them together with an additional booster stage (MOS input, so the ADUM is really only used for isolation + desat). The problem occurs in only some identical setups when the respective converter's transferred power/current exceeds a certain threshold. Unfortunately, I tied together all FAULT and READY pins so I can't tell which pin is signalling the error. The basic data is:
- VDD1 = 5V
- VDD2 = 12.7V, bootstrapped --> highside about 12V
- VSS2 connected to GND2
- GATE_SENSE tied to VSS2
- VOUT_ON connected directly to VOUT_OFF and the booster's input pin (~13cm trace length, can't be changed unfortunately).
I tried out the following things:
- measured the error output to see if it was some noise my control was picking up. No noise, it's really going low like if it was pulled low.
- monitored DESAT voltage --> not surpassing 6V, problem gone while differential probe was attached
- removed the measuring equipment and soldered pins 9, 10, 11 together directly at the ICs --> DESAT should be disabled, problem was back however
- replaced the original single 22u/25V X5R VDD2 capacitor by 100n (at the bottom) + the original 22u piggy-backed onto the 100n almost directly between pins 13 and 11 (~3mm trace length each side), problem persisted
- measured VDD2 using a differential probe. Apart from some high-frequency ringing I would attribute to the measurement setup, the voltage never seems to go below 11.9 V --> well away from 11.1 V which is given as the negative-going threshold in the datasheet for UVLO
- increased VDD2 by 0.5V. No change in behavior.
One very strange thing is that when I had the differential probe attached to VDD2 and/or DESAT, the problem disappeared. I thought maybe the parasitic capacitance of my probe was helping so I soldered a small capacitor (47p) between the highside-VSS and the lowside-VSS (directly adjacent on my board). Didn't help.
Also, the problem did not return when I removed the probe but left the short (~4 cm) cables used to connect the probes before. The cables were soldered to the CBlank capacitor and the VDD2 capacitor. I started fiddling with the cables and found out that two cables on each high side ADuM sufficed to make my problems go away. The cables needed to be bent over the IC in roughly its center. So I thought it might be some kind of electrical field problem which got "shielded" by the short cables. I then cut out a copper foil to match the IC's size plus two "pins" and used those "pins" to solder the foil to the IC pins 16/15 and 9. I thought that this would be a much better solution than the cables however the problem was back! Both dv/dt and magnetic field at the ICs' place shouldn't be greater than 1/50 of the critical values given in the datasheet if calculated by the di/dt in the load and the dv/dt using the output stage's capacitance and the load current.
I'm really running out of ideas here and would be very grateful for any suggestions what else to try out.
Best regards
Lennart
