[ADuM7223]How to design High-Side voltage when MOSFET gated 200V?


I would like to know about H-Bridge driver circuit with using ADuM7223.

According to


I understood VDDA and VDDB should be separate supply, but I cannot find any reference circuit.

I also refer to


Is there any information how to VDDA supply when Vbridge voltage max 200V? (This apps note Vbridge is about 16V.)

Actually, one customer had designed with following above pdf Fig.1 with using ADuM7223 instead of ADuM7234 and Vbridge is 200V.

But High-side voltage output is only about 5V instead of 200V.

Thank you for your help in advance.

Best regards,


  • 0
    •  Analog Employees 
    on Aug 13, 2015 9:34 PM over 5 years ago

    Hello Sofy,

    There are two important voltages to talk about when discussing H bridge topologies and gate drivers. The first votlage is the actual gate voltage for the gate drivers. This is usually constrained to ±20 V due to the abs. max of standard silicon MOSFETs right now. A normal gate drive voltage could be from 0 to 15 V. This is the voltage that is delivered by the gate driver to the MOSFET between the gate and the source.

    The Vbridge voltage is the other important number to care about. This is the bus voltage that the H bridge feeds to the system. The problem in https://ez.analog.com/message/129916#129916 was that the bridge voltage was much larger than the gate voltage swing, so a floating supply for the high-side needed to be used, which is why the ADuM3223 family was suggested, instead of the ADuM3220, which has dual outputs, but only one isolation region on the secondary side. Imagine the case where the high-side switch is on, and the low-side switch is off. The middle of the half-bridge would swing to 75 V, meaning the VOA of the ADuM3220 could not keep the high-side on since it is being fed by a 12 V supply referenced to ground.

    In order to obtain the floating power supply for the high-side, there are a few options, and whether the options work depend on the application. One of the most widely used setups is the bootstrap configuration, if the application has a sufficient minimum duty cycle and switching frequency. This creates a temporary floating supply out of a bootstrap capacitor that is sized sufficiently to output the needed drive during half a cycle of operation. This basically just costs a diode and a slightly larger capacitor near the decoupling capacitor of the high-side VDDA.

    The other main option is to use a dedicated isolated supply to feed the high-side output. This usually costs more board space and component cost, but frees the designer from duty cycle and frequency constraints. The actual construction of the dedicated isolated supply varies greatly from designer to designer. If rough regulation of the gate voltage is acceptable, a multi-tapped flyback or forward converter is sometimes used. Multiple unregulated outputs could feed multiple high-sides in a multi-phase system.

    Fig. 1 of the H-bridge app note is using a bootstrap configuration:

    The ADuM7223 is well suited for this application. There are a few tricky things to watch out for during testing. The first is that the output gate drive of the high-sides while the bridge voltage is on have to be measured while the system is switching. This is because the bootstrap setup refreshes itself each cycle. Secondly, the GNDA connections will swing to Vbridge each cycle, so differential probes with sufficient common mode range should be used to measure the output voltage. Otherwise, two ground referenced probes can be used measuring VOA and GNDA and using subtract on the scope.

    The comment "But High-side voltage output is only about 5V instead of 200V." has me a little confused. The VOA output should only expect to output the same voltage that is applied at VDDA to GNDA. The difference is the GNDA is allowed to float up with the half-bridge voltage.

    If VOA to GNDA is only outputting 5 V, check to see that the VDDA to GNDA capacitors are sufficiently large to hold the voltage up during the half cycle. The bootstrap capacitors will be charged up close to the VDDB to GNDB voltage when the lowside is on (minus a diode drop).

    Here is a link to an article about possible ways to power the high-side drive:



  • 0
    •  Analog Employees 
    on Aug 18, 2015 1:04 PM over 5 years ago

    Hello, RSchnell-san,

    Thank you very much for your detailed response!

    I understood that.

    I would ask to the customer.

    Best Regards,


  • Hello,

    Sorry for reactivating an older question. Does this mean that VGS of the transistor could be negative, due to the floating of GNDa? More precisely, is this driver suitable for SiC transistors that need +15~ -5 VGS?

    Thank you in advance.

  • 0
    •  Analog Employees 
    on Oct 18, 2017 11:44 PM over 3 years ago


    Yes, the Vgs voltage relative to the source node can be run negative since GNDa is floating. This is one of the advantages of digitally isolated gate drivers as compared to high-voltage level shifters. The VDDA/VOA/GNDA pins are on one silicon die, and the VDDB/VOB/GNDB pins are on a totally separate silicon die. If you wanted, the B region could be used as a high side, as there is no differentiation between the A and B with respect to what needs to be at a lower potential.

    The ADuM7234 has a recommended VDDA/B range that goes to 18 V, so +15, -5 is too much for it (since this is 20 V total). Parts that will work with this range are the ADuM4120, ADuM4121, ADuM4135, and ADuM4136.

    One nifty way to obtain the negative rail is to supply a 20 V source for the gate driver secondary side, but split it into two effective rails using a Zener diode. Here is a a figure to help the discussion:

    We can see here that the VDD to GND voltage is V1 + V2. The Q1 gate to source (Vgs) will swing from V1 to negative V2. From the gate driver's perspective, it only sees a unipolar supply (V1 +V2), but the gate voltage delivered to Q1 sees a bipolar supply!

    Here is the same circuit shown with one possible zener diode configuration:

    Dz in this example would be a 15 V Zener. Rz should be chosen such that there is enough current to sustain the switching gate drive current. V3 in this example would be 20 V to support the +15 V, -5 V target you mention. You could also swap the placement of Dz and Rz, using a 5 V Zener to create the negative rail as well. The main cost of this implementation is added quiescent current draw on the isolated power supply.

    For SiC, I would recommend the ADuM4121. It has an integrated Miller clamp, and a wide output voltage range that is compliant with most SiC requirements. Additionally, its CMTI rating is very high, at 150 kV/µs, which is sufficient for almost all SiC devices on the market today. My second choice would be the ADuM4120. It is a 6 pin gate driver, and has the same high CMTI rating as the ADuM4121, but no Miller clamp. Since one of the main reasons to drive a gate negative is to avoid accidental Miller induced turn on, using a part without a Miller clamp is a viable option. Single channel devices allow for easier layout, which is very important for the wide bandgap devices today.

    One thing to note is that if you are making a bipolar operation from a unipolar supply, bootstrapping becomes interesting to say the least. Since the lowside switch is used to ground the highside, we only really get to charge the positive voltage of the highside. Due to the complexity of describing how to setup a bipolar bootstrap, right now I'd recommend using an isolated DC/DC converter for the +20 V supply. That also frees you up from duty cycle and frequency minimums forced upon a bootstrap design.