Our customer needs reinforced insulation with ADuM6402.
They prefer to use Single Overlap Stitching Capacitor.
Is this OK for reinforced insulation?
Thank you for the advice.
I heard ADI found new layout technique to minimize EMI. Some of ADKK guys seemed to heard it at Limerick training.
Is this to use ferrites on the Viso and GNDiso?
We looked into this and put together a drawing that shows 2 methods of obtaining reinforced with a single overlap of stitching capacitance:
1. For reinforced with a thick single layer 0.4mm FR4 between the copper to obtain reinforced.
2. Using 2 layers of FR4, each layer tested together at the required voltage. Recommend each layer is capable of full required withstand voltage.
Note: To reduce emissions with isoPower it may be hard to get the needed stitching capacitance as detailed in AN-0971, with a thick FR4 layer, especially at 0.4mm. Additional techniques using ferrites on the Viso and GNDiso may needed.
Thank you. I think I received it before.
Power-man: Yes, this is using ferrites on Viso and GNDiso. This information eventually will be added to the app note on AN-0971 on isoPower emissions. I can send a PPT to you by email on this preliminary information.
The customer has a question about your comment.
The customer wants to know "Using 2 layers of FR4, each layer tested together at the required voltage. Recommend each layer is capable of full required withstand voltage" in detil.
Does this mean the PCB should be tested by itself without mounting devices?