We have been using an ADN4694 half-duplex, M-LVDS transceiver in a design. It's worked fine until recently.
When the receiver is enabled by asserting #RE, a positive glitch (a solid output high voltage approximately 50-200ns) appears on the receiver output, RO. There is very little delay between the #RE falling edge and the start of the glitch. No glitch occurs when the enable #RE is tied to ground. Power/ground look solid at the component pins.
The glitch is observed with the LVDS inputs static with no cable connected; hence the problem is not related to bit patterns or cabling. The RO output is disconnected from the inputs it drives, to rule out the glitch coming from elsewhere. The glitch occurs at random locations within the 4 data channels in the product, and across multiple units.
Any comments / suggestions? At this point the glitch really appears to be generated on the die level. Thanks!