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ADN4694 M-LVDS enable glitch

We have been using an ADN4694 half-duplex, M-LVDS transceiver in a design.  It's worked fine until recently.

When the receiver is enabled by asserting #RE, a positive glitch (a solid output high voltage approximately 50-200ns) appears on the receiver output, RO.  There is very little delay between the #RE falling edge and the start of the glitch.  No glitch occurs when the enable #RE is tied to ground.  Power/ground look solid at the component pins.

The glitch is observed with the LVDS inputs static with no cable connected; hence the problem is not related to bit patterns or cabling.   The RO output is disconnected from the inputs it drives, to rule out the glitch coming from elsewhere.  The glitch occurs at random locations within the 4 data channels in the product, and across multiple units.

Any comments / suggestions? At this point the glitch really appears to be generated on the die level.  Thanks!

  • Hi Ken,

    In order to help you I would like to know a bit more about your application and glitch issue.

    When you say 'It's worked fine until recently' what exactly do you mean ?

    Was the design completed and working OK when installed in its application environment?

    Perhaps the ADN4694E units in your application were damaged, by an EMC event for example.

    ........One way to confirm this is:

    Have you performed measurements on units installed in your design?

    Or have you performed measurements on previously unused units from stock ?

    Can you please provide an oscilloscope plot for the RO glitch observed, and a circuit diagram (any resistors on any pins?). Does the RO glitch occur on Vcc power-up of the ADN4694E ? Is the driver disabled at the same time as the receiver is enabled?

    Have you seen glitches on other pins?  You have stated: 'The glitch occurs at random locations within the 4 data channels in the product'.

    Best Regards,

    Richard

  • Hi Richard,


    Disregard my "worked fine until recently" comment.   The transceivers are used in the data backbone of an avionics system (non-critical function).  Three half-duplex buses carry data between the head end unit to 3 strings of distribution units. A fourth bus interconnects with other head end units.  The buses are a "repeater" topology, not multidrop.  Although field complaints of sluggish response began a few months ago, we now feel the issue has always existed for the 2 years the system has been in service.  The receiver output glitches are observed in the head and satellite units both on the aircraft and in a more controlled benchtop environment.

    We replaced the components with new ones, avoiding any possibility of handling or testing damage.  The new parts still show the same problem, as do previously assembled units fresh from stock.  An equivalent TI part has the same problem, though less severe.

    Vcc/Gnd are steady state during the glitch event.  Placing a 10uF bulk cap directly across the power/ground pins does not help.

    The Rx output (RO) is the only pin that glitches.  Note in the schematic snippet that #RE and DE are tied together via 0 ohms.  However when #RE is independently asserted the glitch occurs, and when #RE is held active low, the glitch does not occur.

    Note in the scope shot the glitch is about 1.6us wide.  Yellow= diff input voltage, Green= #RE input from FPGA, Purple= RO showing active high glitch.  Changing the cable and termination characteristics varies the character of the glitch.  Regardless of duration it consistently goes away approximately 150us after #RE falling edge.

    Permanently grounding #RE so the receiver is always on appears to be a solid and easy fix.  However we want to get to root cause.  Gut feel right now is some event on the diff input causes the glitch, though we aren't able to see anything on a pretty good o'scope.  Does the receiver have a "stabilization" period after being enabled where it's vulnerable to upsets from the input (similar to metastability in a digital component)? 

    Thank you for the help!

  • Hi Ken,

    Thanks for providing further detail, and sorry for the delay in getting back to you on this.

    There are three cases I could expect RO to be output high, (a) if the differential voltage (Vb - Va) is >=150 mV, (b) high sometimes where the differential voltage is between 50 and 150 mV (receiver output undefined), or (c) where /RE is high and there's a pull-up on RO (RO is high-Z when /RE is high).

    I suspect that somehow this is case (b). Channel 1 and 4 in your oscilloscope plot seem to be similar, are these Va and Vb? (it doesn't seem likely as that would imply a mostly 0V differential). If Channel 1 (yellow) is the differential voltage Va - Vb, I would expect it to alternate positive and negative (logic 0 and logic 1). If it were always >150 mV as the plot seems to show (161 mV to 659 mV), then RO would be expected to always be high.

    Could you capture an oscilloscope plot that has a single ended probe on A and one on B, along with RO and /RE, so we can clearly see whether RO matches what the differential voltage implies?

    ADN4694E is a Type 2 MLVDS receiver, so it has a receiver offset but no hysteresis - if the differential voltage changes too slowly around 50 to 150 mV, then there can be chatter/noise on RO (kind of like what we see after the pulse high in your plots - that's another reason that I'd like to better interpret the A and B voltages for myself at that point in time).

    Best regards,

    Conal

  • Hi Richard,

    Sorry about my long delay.  The engineer had to set this on the back burner; he agrees with your comments and request.  I have attached his scope shots and summary.   Although the receiver has no hysteresis and RO state is "undefined" in the failsafe zone, we'd still expect a solid Vol or Voh as long as differential input voltage doesn't cross the threshold.   The glitch seems to be triggered by simply toggling #RE; there's no glitch when #RE is permanently enabled.  That would not seem to be the case if input noise was the cause.  Thanks in advance for your comments / assistance!

    Ken

  • Hi Ken,

    Thanks for gathering additional information.

    For where the bus differential voltage is 0V, this should result is a logic high output RO = high.

    (see Figure 11 M-LVDS Type 2 Receiver Output in AN-1177)

    http://www.analog.com/media/en/technical-documentation/application-notes/AN-1177.pdf

    Figure 2 in the Word report that you attached shows that this is the case.

    However, then there is some noise on the VA, VB, VDIFF bus lines (Figures 2, 3). This VDIFF noise occurs in the 50mV to 150mV undefined region for the receiver. Hence we see the noise on the RO channel. For where VDIFF is in the region 50mV to 150mV the output is indeterminate.

    Have you investigated the source of the noise on the VA, VB channels?

    Best Regards,

    Richard

  • Hi Ken,

    Just to correct a typo in my previous reply.

    This should read: Where the bus differential is 0V, the Type 2 MLVDS should have RO low.

    However, the comments regarding the RO output noise/chatter are valid in my previous reply.

    Have you investigated the source of the noise on the VA, VB channels?

    Best Regards,

    Richard

     

  • Richard,

    The noise in the scope shots is due to scope probe grounding.  It's difficult to physically probe the inputs in an ideal manner.  In any case, Vdiff doesn't cross the threshold.  More important, there is no output glitch with #RE tied to ground.  If input noise were the cause, the output glitches would still be expected regardless of #RE tied low or driven low.

    The core issue is why the RO output glitches only when #RE transitions, and not when #RE is static.  Also, a pin-compatible component from a different manufacturer has the same behavior but far shorter duration.

    This seems to be something on the die level...we've fixed the problem by tying #RE permanently low, but really want to understand root-cause.

    Thanks,

    Ken Ishiguro

  • Hi Ken,

    The oscilloscope plots you provided show VDIFF noise in the range +/-100 mV, and up to +/-200 mV in some plots.

    The Type 2 receiver input threshold is +50mV min, and +150mV max.

    In this situation you would expect to see unreliable receiver output data for some cases.

    For the customer application is it acceptable to put /RE permanently low?

    Regards,

    Richard


  • Thanks for the speedy reply, Richard.

    As explained in my replies to your questions, the Vdiff noise is a measurement artifact and not actual differential noise on the input.  The A-B trace shows this, and empirically the output glitches do *not* occur with #RE held low.  If there were >100mV differential input noise this would presumably show up on the output with #RE held low.

    Instead, the noise is induced by the falling edge of #RE.  We have band-aided the problem by permanently grounding #RE  which is OK in the application as commented above.  At this point we're seeking a root-cause explanation of why  #RE transitions trigger the output glitches when Vdiff= 50~150mV but not when #RE is static.

    Thanks,

    Ken

  • Hi Ken,

    Sorry for all the questions to date. But we really haven't seen behavior like this before using the ADN4694E.

    What is the competitor part number that you mentioned that also displays the same behavior?

    Looking at your posts - can you please provide a better resolution schematic? I can't make out the part numbers for the image that you provided.

    When performing your testing are the ESD protection components attached to the A, B bus lines?

    How much of a capacitive load do these ESD protection components present to the ADN4694E A, B lines?

    We could possibly perform some lab measurements, but I need to confirm your lab setup firstly.

    To correspond more on this issue please use my personal email address:

    Richard.Anslow@analog.com

    Regards,

    Richard