We are currently developing a 6-layer PCB board to be compliant CISPR 22 class A limits with:
- ADUM5010 with 5.8mA@5V
- ADUM5010 with 1mA@3.3V
- ADUM5010 with 0.25mA@3.3V
- ADUM3151 SPI 15MHz 3.3V
- ADUM3151 SPI 500kHz 3.3V
- ADUM7240 / ADUM7643 100kHz 3.3V
We have read AN-1109 and AN-0971 and we have actually deduced that:
Layer PCB Emissions: 47dB (125MHz) - 58 dB (250MHz)
Class A Limits : 40 dB (125MHz) - 47 dB (250 MHz)
Required EMI reduction: 7dB (125MHz) - 11 db (250 MHz)
We are assuming that the following EMI reduction design is valid for both
ADUM3151 (10MHz) and ADUM5010:
L = 0.015m
w = 0.010m
Coverlap = 50pF
moreover by introducing interdigitating stitching over 4 layer we have:
Ctot = 50pF x 2 = 100 pF
To meet required EMI reduction we add safety capacitor
C = 100 pF
Finally we have Cstitching = 200 pF with desired EMI reduction according
to AN-0971-Figure 20
Do you agree with this designing approach?
Is it necessary to use also Edge Guarding technique?
Is this EMI reduction configuration valid for both ADUM3151 (10MHz) and ADUM5010?
Have you any suggestion for Minimizing Radiated Emissions from Multiple isoPower Devices in Dense PCB Layouts?
Your approach seems good in general for treating emissions. I would like to see your schematic and layout to understand your application more. If you like, we could be do this with emails.