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Standard digital isolator for I2S audio line

Hi,

We are now studying to use ADI standard digital isolators for I2S, not I2C-bus but Inter-IC sound bus, replacing for legacy photo couplers.

One considering I have is I2S is seemed to be specified as TTL type of logic which VIL=0.8V and VIH=2.0V, subject to I2S bus specification of Feb.1986 (but it notes: <At present, TTL is considered a standard for logic levels. As other IC (LSI) technologies become popular, other levels will also be supported>, however I can not find out any newer specifications, so far), against ADI isolator seems to be using CMOS logic level.

Could you please make sure whether ADI's standard digital isolators are suitable for insulation in I2S digital audio lines ?

Or, if you provide any note of caution when using isolators in I2S lines, it would be very much appreciated.

I may add that devices of our interest are, for example,  ADuM751x, ADuM348x, ADuM228x, ADuM128x or others. 

Best Regards,

  • Hello Takehisa,

    I have not looked into the I2S bus before, so I pulled down the standard and had a look.

    As you point out this standard is written around TTL logic levels.  Our first generation isolators ADuM130x, ADuM131x, ADuM140x, ADuM141x use TTL logic levels for their I/O buffers, and should be compatible with your application.  Our newer products use CMOS logic, but for an audio application, their performance should be very adequate.

    Was there a specific performance goal you are considering the parts listed in your inquiry?

    Best Regards,

    MSCantrell

  • Hi MSCantrell,

    Thank you very much for your reply and concerning.

    At first for your question, target performance is 5~6 Mbps in current design, however it may increase to around 20 Mbps in near future of our scope.

    Next, sorry to bother you again, there are several additional questions.

    a) If using newer CMOS isolators, do we need or better to add any level adjusting between I2S and both side of CMOS isolators ?

    b) For example ADuM7510 datasheet specify Maximum Data Rate under CL=15 pF, however when CL is bigger, assuming Maximum Data Rate has to be decreased but how do I estimate or calculate it ?

    c) What if it needs level adjusting in above a), does it affects to Data Rate which can be achieved ? 

    Again, your helps and support would be very much appreciated.

    Best Regards,

  • Hi,

    Could you please reply or clarify to my questions ?

    Your support would be very much appreciated.

    Best Regards,

  • Hello Takehisa

    Our isolators are al built on CMOS processes, it is a choice at design time if we adjust the switch point to be for TTL input ot CMOS input levels.

    Whether to add translation buffers or not depends on what you have on the bus.  Our parts with CMOS outputs will be compatible with the TTL inputs, but other devices talking on the bus may or may not be able to supply a VOH high enough to guarantee that we can read it as a high level.  If you have components that can not drive the line to 0.7xVdd, then you may need a level shifter.  I would review the other components output specs in detail if you want to use a component like the ADuM7510.

    If CL is larger than speced, you can get a good idea how the output will respond by knowing that the channel impedance of our outputs is about 70ohms, you can make that part of an RC network that pulls the line up or down.  It is a bit crude, but it will tell you if you need to worry.

    Level shifting will have some propagation delay I am sure, so it needs to be examined.

    I hope this helps.

    Best Regards,

    MSCantrell

  • Hi MSCantrell,

    Thank you very much for your kind and suggestive reply.

    Especially, your answer regarding to CL is something beyond I had foreseen, however it is really good study for me to imagine analogy between behavior of isolators and RC filters.

    Thank you again for your support. I may have a chance to talk about more detail of the issue which bred source of my question.

    Many Thanks,