Jitter specifications of ADN4661

Hello,

We tried to use the ADG3241 as the clock buffer supplied to the AD9257.

But the jitter is large, so we should consider immediately a different device.

We expect that the ADN4661 can use instead of the ADG3241.

Please  let me know jitter value of ADN4661.

(Our expectation is jitter less than 0.25ps@20MHz.)

We must get this answer in July 18th in japan time.

I'm sorry, Please help as soon as possible.

Thanks,

Tak

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  • 0
    •  Analog Employees 
    on Jul 18, 2014 12:18 PM over 6 years ago

    Hello Tak-san,

    Can I confirm that for this application, you are concerned with additive phase jitter (phase noise integrated across a frequency range of e.g. 12kHz to 5 MHz, for a carrier freq of 20 MHz)?

    Unfortunately we do not have this jitter data for the ADN4661, and particular lab resources and equipment would be needed to make these measurements, so there would be a delay if we were to find out typical performance. Note that ADN4661 is not an LVDS buffer, it is an LVDS driver only (LVTTL single-ended input).

    We do have additive phase jitter specified for the ADN4670 LVDS clock buffer, although this is also a 1:10 fanout for clock distribution. Is this suitable for your application? Additive phase jitter for the ADN4670 is 281 fs @ 30.72MHz, which is close to your requirements.

    In your circuit, what provides the clock for the AD9257? Maybe this would help us to understand your requirements for an LVDS driver to the AD9257 clock inputs, allowing us to suggest a suitable part?

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  • 0
    •  Analog Employees 
    on Jul 18, 2014 12:18 PM over 6 years ago

    Hello Tak-san,

    Can I confirm that for this application, you are concerned with additive phase jitter (phase noise integrated across a frequency range of e.g. 12kHz to 5 MHz, for a carrier freq of 20 MHz)?

    Unfortunately we do not have this jitter data for the ADN4661, and particular lab resources and equipment would be needed to make these measurements, so there would be a delay if we were to find out typical performance. Note that ADN4661 is not an LVDS buffer, it is an LVDS driver only (LVTTL single-ended input).

    We do have additive phase jitter specified for the ADN4670 LVDS clock buffer, although this is also a 1:10 fanout for clock distribution. Is this suitable for your application? Additive phase jitter for the ADN4670 is 281 fs @ 30.72MHz, which is close to your requirements.

    In your circuit, what provides the clock for the AD9257? Maybe this would help us to understand your requirements for an LVDS driver to the AD9257 clock inputs, allowing us to suggest a suitable part?

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