I'm using the ADUM1401 in an application where VDD1 is up long before VDD2. VID is pulled up to VDD2 and when I monitor this signal during startup I can see it following VDD2 as expected.
When looking at VOD, this signal is high when VDD2 is unpowered. But during the ramp up of VDD2, a short (5-10 µs) glitch occurs on VOD, which is undesired, because this goes into a falling-edge triggered circuit. What is the cause of this glitch and is there any way to prevent this?
Apparently, the issue was solved with the ADUM3401 on one of the proto boards.
On another board, this issue is still present: a small 1µs dip on the output when the input powers up.