ADM3053 question

Dear sir

   I meet a problem when using ADM3053, the original can bus interface is NXP TJA1040  and is replaced by ADM3053. In the following picture, I follow the ADM3053 application note to design my circuit and the can bus front and back end are all the same as before. But the performance isn't good, Rx can receive the signal but isn't continue transfer the Tx signal, I doubt the problem is came from the canH and canL, Could you give me some advice to correct it.

  • 0
    •  Analog Employees 
    on Aug 2, 2013 12:58 PM

    Hi kj.liu,

    In order to help you with your question i will need some more details.

    Can you please provide me with an oscilloscope plot with CANH, CANL, and RXD?

    Can you please tell me the data rate used in this application?

    What is the application used for? And how many units of this applicaiton will be produced per year?


  • Hi Ranslow

        I am distributor FAE and it's a case my customer meet , this application is used in automotive BMS(battery monitor system) to communicate with MCU and I think the quantity is around 10k/y. Now because my customer is busy on other thing , so I only can show you the waveform he draw to me. Base on this picture, the pin CanH and CanL waveform is fine but in Can H1 and CanL1, the waveform become stranger (like picture shown) and affect the RX signal. Even remove the element between the CanH,CanL and CAN H1 and Can L2( put the oscilloscope signal in Can H1 an L1 directly , just the datasheet application shown) .

         I have searched related ADM3053 question reply, Does the customer use 2 layer PCB could induced this result? Because I think the circuit looks is fine. Thank you!

  • Hi RAnslow,

        I think I might know the reason why cause but need your confirm. The original design is using TJA1040 and it has a pin name SPLIT. This pin function sets a reference voltage between CANH and CANL to avoid error frame. If we transfer this design to ADM3053, there is no pin to set a reference voltage, so my customer connected the Vref pin on ADM3053 between CANH and CANL  (the original SPLIT position). it would cause the problem I say before.what's your though?

       There is one more question, if we can't set the reference voltage, does the error frame be affected or this function already build into the chip? 



  • 0
    •  Analog Employees 
    on Aug 15, 2013 6:23 PM

    Hi KJ,

    It's difficult to assess without an oscilloscope plot, but the hand-drawn waveform suggests that the edges are a bit too slewed. Looking at the schematic, pin 18 (RS) is connected to ground through 10kOhm. This will mean the ADM3053 is operating in slope control mode, with the edges intentionally slewed to some degree (the connection to Vref might affect this also). This mode supports lower radiated emissions and reflections at lower data rates.

    What data rate is used here? For data rates towards 1 Mbps it's best to operate in full speed mode (RS pin directly to GND2).

    The ADM3053 does not require additional external biasing of the recessive bus voltage level with a SPLIT connection or similar. I'd recommend disconnecting Vref, but do leave the common mode filter capacitor (4.7uF).

    Best regards,