any solution for lvds driver from FPGA

Hello Niulian,

If I understand correctly, you want to buffer the LVDS outputs from the FPGA in order to drive them across a longer distance?

What distance do you want to drive across, and at what clock/data speeds? What is at the receiving end?

The ADN4670 acts as a buffer suitable for LVDS clock signals up to 1.1GHz. This also provides 1:10 fan-out, but unused outputs can be disabled.

Alternatively, an LVDS receiver such as ADN4666 (or ADN4662/ADN4664/ADN4668) can be connected to the FPGA outputs, and then an LVDS driver such as ADN4665 (or ADN4661/ADN4663/ADN4667) can be connected to the ADN4666 receiver outputs.

Best regards,

Conal

Hello Niulian,

If I understand correctly, you want to buffer the LVDS outputs from the FPGA in order to drive them across a longer distance?

What distance do you want to drive across, and at what clock/data speeds? What is at the receiving end?

The ADN4670 acts as a buffer suitable for LVDS clock signals up to 1.1GHz. This also provides 1:10 fan-out, but unused outputs can be disabled.

Alternatively, an LVDS receiver such as ADN4666 (or ADN4662/ADN4664/ADN4668) can be connected to the FPGA outputs, and then an LVDS driver such as ADN4665 (or ADN4661/ADN4663/ADN4667) can be connected to the ADN4666 receiver outputs.

Best regards,

Conal