ADuM5402, state of logic output when power is not well supplied

Hi,

We are assuming what would be occured when power supply from primaly side is stopped by any reason during operation, for example, malfunction at internal or external circuitry, at ADuM5402.

In this case, how is the state of primary/secondary side of output pins supposed to be ?

 

Subject to page.24 of datasheet, POWER CONSIDERATIONS, we are assuming output become to be high-impedance, but it can allow to understood that it may be default low, or remain state just before power down.

Especially following last phrase are not clear to see...<The outputs on the secondary side hold the last state that they received from the primary side. Either the UVLO level is reached and the outputs are placed in their high impedance state, or the outputs detect a lack of activity from the primary side inputs and the outputs are set to their default low value before the secondary power reaches UVLO.>

If you provide another explain by focusing a case power supply suddenly stop during normal operation, it would be very much appreciated.

Best Regards,

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  • 0
    •  Analog Employees 
    on Apr 25, 2013 12:15 AM over 7 years ago

    Hello Usaghi

    Keep in mind that the two sides of any isolator can work somewhat independently.

    The secondary side normally gets its power from the isoPower transformer.  It regulates the voltage by sending a digital control signal to the primary.  This provides power to the digital channels on the secondary.  If power from the primary is interrupted, the output voltage will fall until it reaches the UVLO threshold (about 2.4V) below that the output buffers are off making the outputs look like a high impedance.

    One exception to that is if there is another source of power on the secondary side, either on the Viso line or at an input.  If Viso is being held up by large caps, or another power supply, then it can act like a power input and provide power to the secondary above the UVLO level, and the secondary data channels will remain active.  They will likely change to the default low state after a few uS since the are presumably not getting any data from the primary side.  A similar thing can happen if digital signals from other chips are present when the isoPower is not.  The digital signals will push current into Viso through the ESD protection diodes and again the secondary can be on in a default low output state.

    So it is not simple behavior if parasitic power is present.

    I hope this is clear.

    Best regards,

    MSCantrell

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  • 0
    •  Analog Employees 
    on Apr 25, 2013 12:15 AM over 7 years ago

    Hello Usaghi

    Keep in mind that the two sides of any isolator can work somewhat independently.

    The secondary side normally gets its power from the isoPower transformer.  It regulates the voltage by sending a digital control signal to the primary.  This provides power to the digital channels on the secondary.  If power from the primary is interrupted, the output voltage will fall until it reaches the UVLO threshold (about 2.4V) below that the output buffers are off making the outputs look like a high impedance.

    One exception to that is if there is another source of power on the secondary side, either on the Viso line or at an input.  If Viso is being held up by large caps, or another power supply, then it can act like a power input and provide power to the secondary above the UVLO level, and the secondary data channels will remain active.  They will likely change to the default low state after a few uS since the are presumably not getting any data from the primary side.  A similar thing can happen if digital signals from other chips are present when the isoPower is not.  The digital signals will push current into Viso through the ESD protection diodes and again the secondary can be on in a default low output state.

    So it is not simple behavior if parasitic power is present.

    I hope this is clear.

    Best regards,

    MSCantrell

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