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ADuM2402CRWZ temperature and output Drive


We are currently using the ADuM2402 with an approximately 27MHz SPI clock rate.

We added LC filters to the output of the ADuM as an EMC mitigation (in addition to stitching capacitance and edge guards on the PCB).

We are noticing some data corruption when the ambient temperature around the ADuM is raised above ~45ºC. removing the capacitance to ground, only 10pF, gets rid of the data corruption even with an ambient temperature of 60ºC. The ADuM is not running near its maximum throughput and track length is very short to the SPI component.

Apart from small latency increases, what else is changing in the ADuM with temperature that makes the chip sensitive to an increased capacitive loading on the output?



  • Hello Ryan,

    It would be helpful if you could provide a schematic and oscilloscope plots of the timing with and without the load capacitance connected. Same plots at room temperature versus 45C may also be useful.



  • Hi Dave,

    Thanks for your response, attached is an except of the schematic with the relevant components. The device is multi channel, this problem appears on some channels and not others, though can be induced by a further significant increase in temperature. The channels are implemented identically. The ADCs share the Vdd and Vref power supplies, otherwise are completely independent (including power supplies for the front end circuitry).


    • Two Channel at 45ºC Data Corruption
      • Manifestation of Data corruption on single channel when ambient temperature raised to 45ºC
    • data ISO CHB at temp is measured at U17 Pin 11 at different temperatures,
      • there is no apparent significant difference in the output.
      • At 25ºC Data is acquired without Corruption
      • At 45ºC if the MSB is 1 then Bit (MSB - 1) will also be latched as a 1
    • data ISO CHB add CAP2 is measured at U17 Pin 11 with a second CRO probe at the intersection of C23 and L8 (ref U17 Pin 9).
      • There is significant ringing on the Data output to the ADuM with additional capacitance
      • This causes the same corruption as seen at increased Temperature (All Filter Caps are NPO, temperature stable to 30ppm/ºC)
    • data clk iso vs ni is measured on U17 at pin 11 & 14 Isolated (iso), pin 3 & 6 Non-Isolated (ni)
      • Clock Measured on Pin 6 is De skewed by 60nS to allow for ADuM Latency.
      • Relative latency of clock and data change by less then 1nS (when measuring Pin 3 & 6) and heating U17, Corruption is present on the output.

    We also measured U17 at pins 11 and 6, The high/low transitions at the input and output of the ADuM match. We have tried changing the clock frequency, sampling clock skew on the FPGA with no effect.

    We have removed and checked the values of the components mounted. The channel which is behaving well at temperature has a slightly higher capacitance and measures as having more ringing on the SDO line then the poorly behaving channel. We have found increasing capacitance on the poorly behaving channel detrimental.

    We know removing C24 allows us to run the device at much higher temperatures without data corruption on this channel, we have also ascertained that this is not specific to the ADuM on this Channel. We are keen to determine the root cause of this data corruption due to raised ambient temperature so we can be confident that any fix applied, and understand why this problem is appearing on some channels and not others.



  • Ryan,

    Thanks for the additional data. I'm a little confused about to of the plots showing U17 pin 11, since that's an input to the ADuM2402. Can you provide these plots:

    • good and bad outputs at 25 C with capacitance
    • good and bad outputs at 25 C without capacitance
    • good and bad outputs at 45 C with capacitance
    • good and bad outputs at 45 C without capacitance

    These should be on a time scale that will show any differences between the signals, particularly the two at 45 C.

    I noticed on several of the plots that the signals are going well beyond the 5 V supply rail. This will forward bias internal ESD diodes and raise the chip supply, which could cause misoperation or damage if it goes beyond the absolute maximum rating. I think you should determine if the ringing shown in the plots is real or caused by excess inductance in the scope ground lead.


  • Hi Dave,


    You were correct, my ground lead was too long, the ringing observed disappears when the ground lead length is reduced to a couple of cm.


    I know that the ringing observed should have caused issues, i'm confused as to why it would cause issues on one channel and not the other.


    Attached are some of the plots you requested. The iso clk and iso data are pins 14 and 11 respectively, ni clk and ni data are pins 3 and 6 respectively.


    "iso clk and data cha good gnd1" is a 'zoom' of" iso clk and data cha good gnd"


    Please note the CRO has a bandwidth of 400MHz (2.5Gs/sec) so i don't trust a time scale of less then 10nS/div. The temperature change is fairly small ~20ºC, according to the  data sheet this will change the latency of the ADuM by ~1-2nS at most. i would not expect to be able to observe this with the CRO.

  • Ryan,

    As we discussed offline, I'll get a local FAE in contact with you to help resolve this timing issue.


  • This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin