What is the maximum SPI clock frequency that can be used with an ADuM3441 that has 3.3V supplies?
With channels A, B and C isolating the clock (SCLK), master out, slave in (MOSI) and slave select signals (CS) and channel D isolating the slave out, master in signals (MISO), the maximum clock frequency is 6.9 MHz. In general, the upper limit on the clock frequency in this configuration is determined by the maximum propagation delay. The master reads MISO on the falling edge of SCLK. MISO is delayed by at least two propagation delays because of the combined delay of MOSI and MISO through the digital isolator. There is additional delay from when the slave reads MOSI to when it outputs MISO. Therefore, the time between the rising edge of SCLK, when MOSI is transmitted to the falling edge of MISO, when MISO is read is 2 x tpd + ts, where tpd is the isolator’s maximum propagation delay (36 ns with 3.3V supplies) and ts is the additional delay through the slave. Ignoring ts, the clock half-period is 72 ns and its frequency is 6.9 MHz.
Higher clock frequencies are possible if the clock is looped back through the isolator and falling edge of the delayed clock is used to read MISO into a different register. Delaying SCLK by twice the isolator’s propagation delay significantly reduces the skew between MISO and SCLK’s falling edge. Refer to the links below for more information on isolating SPI with iCoupler digital isolators.