Hello ADI team,
I am using the ADV7619 HDMI receiver and would like to understand the expected clock jitter performance.
My application uses HD video with a 74.25 MHz pixel clock.
Assuming:
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PCB layout follows the ADV7619 reference design,
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power supplies are clean and within specification,
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HDMI source is compliant,
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LLC DLL is correctly configured,
could you please provide guidance on the following:
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What is the expected HDMI input clock peak-to-peak jitter range that the ADV7619 can properly receive?
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What is the typical or expected LLC output clock peak-to-peak jitter at 74.25 MHz?
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Has anyone measured ADV7619 LLC output jitter below 300 ps peak-to-peak under good PCB and power conditions?
In my board measurement, I observed approximately 500–600 ps peak-to-peak jitter on the LLC output. My downstream device requires less than 300 ps peak-to-peak jitter to achieve SMPTE-compliant SDI output.
I would like to understand whether this jitter level is within the expected performance range of the ADV7619, or whether I should investigate another HDMI receiver solution.
The ADV7619 datasheet does not specify LLC output jitter, so any typical measurement data or recommended design target would be very helpful.
The LLC output is used as the pixel clock for an SDI transmitter, so understanding the expected timing margin is important.
Thank you.