LTM2881HV-3 EMI issues

Hello Jordi,

   From an EMC perspective you can conceptually consider an isolated supply as a common mode current source which is connected between the two sides of the isolator and that feeds/drives a dipole antenna created by the two voltage domains/sides of the isolator.   To reduce the emissions you need to reduce the common mode current, prevent the current from flowing into the antenna or reduce the effectiveness of the antenna.  Since it appears that you're already using the 3V version of the LTM2881, you've reduced the common mode current source's current as much as you can with this part, so we'll focus on the other two mitigation strategies.

   A stitching capacitor is intended to prevent the common mode current from flowing into the dipole antenna by providing the current an alternative and lower impedance path to flow.  The dipole antenna's radiation effectiveness can be reduced by reducing the effective size of the antenna arm which detunes it and reduces emissions.  Adding sufficient common-mode series impedance effectively "breaks" or cuts off the dipole antenna arm.  Properly implemented, series ferrites are effective for this purpose.

    Looking at your PCB layout, I'm not clear if the ferrite beads you're mentioning are in the R99/R101 pads or L6 pads, but either way their effectiveness as a common mode filter is negated by the large GNDISO plane which appears to be connected to the external GND/Shield of the cable via C92/R102.

   I believe that you will see a noticeable improvement by reducing the size/area of the GNDISO plane and making sure that all signals (A,B AND GNDISO) are connected externally through ferrites.  For maximum benefit, the ferrites should have no copper under them since this copper layer and the ferrite itself forms a parallel parasitic capacitor that reduces the series impedance at exactly the frequency the ferrites are trying to add impedance.  Also note that larger (longer) ferrite packages will be more effective than smaller packages.  It looks like you have some room for a larger ferrite (especially if L6 is rotated 90 deg.).  I would suggest creating an additional isolated side GND node ("GND2") which is connected to your GNDISO via the ferrite.  See the following markup (you may need to zoom in to see my annotations in white):

   In this markup, I'm assuming that R99 and R101 are actually ferrites and I drew an inductor where the new GND2-GNDISO ferrite might be located.  If R99/R101 are series resistors, then I'd locate the ferrites in R99/R101's location and have the series resistors between the ferrites and L6.

  Also, I'm not seeing any connections to the isolated supply's output other than to C91 so I've not suggested a ferrite on the supply node.  If you do have circuitry connected to this which isn't show in the PCB image (e.g. your comment above about VISO), then you should have a ferrite in that as well.  This ferrite would be in the same area as the other 3.  Also make sure that anything connected to the filtered supply pin is also connected to the filtered GNDISO so that you don't "short" out the CM filter...

  I'd remove the copper on the left and right sides of the LTM2881 and suggest that there be a gap between GND2 and GNDISO copper equal to (or slightly greater than) the pad-pad spacing of the ferrites.  This will minimize the parasitic capacitance between GND2 and GNDISO.  The benefits of going much larger for the plan spacing will be limited by the pad-pad capacitance of the ferrites.  

   To be effective, the stitching capacitance needs to have a low impedance at the relevant frequencies so that the high frequency common mode currents flow through the capacitor and not into the dipole antenna formed by the two voltage domains (e.g. GND1 and GND2).  Also the currents flowing through this capacitor should have as short a path as possible so that their path doesn't inadvertently create a loop antenna.  For these reasons, the stitching cap should be placed next to the part similar to the markup's additional capacitor. 

  I understand that including embedded stitching capacitor structures into a PCB layout can be tricky, but when properly implemented, they are very effective and in many situations they are required, especially if the problematic frequencies are higher (and above the effective self-resonant frequency of a discrete stitching capacitor).  I don't know what you have on the the other layers of the PCB, but usually stitching capacitors can be implemented in 4-layer boards and with a 6 layer board there are more options. 

   Note that if you have other circuitry under this part in this area that I'm not aware of, this could be an issue since those structures could provide an alternative path for the common mode currents to radiate and make the mitigations I've described ineffective!

  In terms of the mitigations you attempted:

• Low EMI mode / nSLO pin - this will address emissions from the bus driver's edge rate which are lower frequency from the emissions that are causing you issues and generally this is more of a conducted emissions issue.
• Low ESL decoupling caps on supply pins.  These can help with issues related to differential mode currents but don't help with the common mode currents that are your problem.   Note that you should be careful about having larger valued caps with low ESL/ESR on supply outputs since this can result in larger ripple frequency currents which have the potential of exciting the loop antenna formed by the cap and traces to the supply output pins.  I don't think this is a likely cause of your emissions, but more is not necessarily better here.
• Ferrite beads on A/B - see above comments
• Grounding connections - I suspect the series inductance of connections is high enough that it is of minimal benefit - your observation of improvement at low frequencies but not higher supports this suspicion.

For your questions:

1. Stitching cap should be between GND1/ GND2 in my image.  Optimal configuration is both discrete cap (larger C for lower impedance at lower frequency) and embedded stitching cap for higher frequencies (lower C, but much lower ESL, so self-resonant frequency much higher).

2. Ferrites - see comments above.

3. While there are differences between different isolated power + transceivers in terms of emissions and ease of mitigation, fundamentally they all share the same mechanism that generates the emissions and so all need similar design techniques.  Regardless of which part you use, you'll still need to have proper layout and EMC considerations - a weak design is going to have issues.  If the LTM2881HV-3 is working for you for other reasons, I would not suggest changing solely because of the emissions.  Following the guidelines/suggestions above, it should be possible to achieve a passing design.

Eric

Hello Jordi,

   From an EMC perspective you can conceptually consider an isolated supply as a common mode current source which is connected between the two sides of the isolator and that feeds/drives a dipole antenna created by the two voltage domains/sides of the isolator.   To reduce the emissions you need to reduce the common mode current, prevent the current from flowing into the antenna or reduce the effectiveness of the antenna.  Since it appears that you're already using the 3V version of the LTM2881, you've reduced the common mode current source's current as much as you can with this part, so we'll focus on the other two mitigation strategies.

   A stitching capacitor is intended to prevent the common mode current from flowing into the dipole antenna by providing the current an alternative and lower impedance path to flow.  The dipole antenna's radiation effectiveness can be reduced by reducing the effective size of the antenna arm which detunes it and reduces emissions.  Adding sufficient common-mode series impedance effectively "breaks" or cuts off the dipole antenna arm.  Properly implemented, series ferrites are effective for this purpose.

    Looking at your PCB layout, I'm not clear if the ferrite beads you're mentioning are in the R99/R101 pads or L6 pads, but either way their effectiveness as a common mode filter is negated by the large GNDISO plane which appears to be connected to the external GND/Shield of the cable via C92/R102.

   I believe that you will see a noticeable improvement by reducing the size/area of the GNDISO plane and making sure that all signals (A,B AND GNDISO) are connected externally through ferrites.  For maximum benefit, the ferrites should have no copper under them since this copper layer and the ferrite itself forms a parallel parasitic capacitor that reduces the series impedance at exactly the frequency the ferrites are trying to add impedance.  Also note that larger (longer) ferrite packages will be more effective than smaller packages.  It looks like you have some room for a larger ferrite (especially if L6 is rotated 90 deg.).  I would suggest creating an additional isolated side GND node ("GND2") which is connected to your GNDISO via the ferrite.  See the following markup (you may need to zoom in to see my annotations in white):

   In this markup, I'm assuming that R99 and R101 are actually ferrites and I drew an inductor where the new GND2-GNDISO ferrite might be located.  If R99/R101 are series resistors, then I'd locate the ferrites in R99/R101's location and have the series resistors between the ferrites and L6.

  Also, I'm not seeing any connections to the isolated supply's output other than to C91 so I've not suggested a ferrite on the supply node.  If you do have circuitry connected to this which isn't show in the PCB image (e.g. your comment above about VISO), then you should have a ferrite in that as well.  This ferrite would be in the same area as the other 3.  Also make sure that anything connected to the filtered supply pin is also connected to the filtered GNDISO so that you don't "short" out the CM filter...

  I'd remove the copper on the left and right sides of the LTM2881 and suggest that there be a gap between GND2 and GNDISO copper equal to (or slightly greater than) the pad-pad spacing of the ferrites.  This will minimize the parasitic capacitance between GND2 and GNDISO.  The benefits of going much larger for the plan spacing will be limited by the pad-pad capacitance of the ferrites.  

   To be effective, the stitching capacitance needs to have a low impedance at the relevant frequencies so that the high frequency common mode currents flow through the capacitor and not into the dipole antenna formed by the two voltage domains (e.g. GND1 and GND2).  Also the currents flowing through this capacitor should have as short a path as possible so that their path doesn't inadvertently create a loop antenna.  For these reasons, the stitching cap should be placed next to the part similar to the markup's additional capacitor. 

  I understand that including embedded stitching capacitor structures into a PCB layout can be tricky, but when properly implemented, they are very effective and in many situations they are required, especially if the problematic frequencies are higher (and above the effective self-resonant frequency of a discrete stitching capacitor).  I don't know what you have on the the other layers of the PCB, but usually stitching capacitors can be implemented in 4-layer boards and with a 6 layer board there are more options. 

   Note that if you have other circuitry under this part in this area that I'm not aware of, this could be an issue since those structures could provide an alternative path for the common mode currents to radiate and make the mitigations I've described ineffective!

  In terms of the mitigations you attempted:

• Low EMI mode / nSLO pin - this will address emissions from the bus driver's edge rate which are lower frequency from the emissions that are causing you issues and generally this is more of a conducted emissions issue.
• Low ESL decoupling caps on supply pins.  These can help with issues related to differential mode currents but don't help with the common mode currents that are your problem.   Note that you should be careful about having larger valued caps with low ESL/ESR on supply outputs since this can result in larger ripple frequency currents which have the potential of exciting the loop antenna formed by the cap and traces to the supply output pins.  I don't think this is a likely cause of your emissions, but more is not necessarily better here.
• Ferrite beads on A/B - see above comments
• Grounding connections - I suspect the series inductance of connections is high enough that it is of minimal benefit - your observation of improvement at low frequencies but not higher supports this suspicion.

For your questions:

1. Stitching cap should be between GND1/ GND2 in my image.  Optimal configuration is both discrete cap (larger C for lower impedance at lower frequency) and embedded stitching cap for higher frequencies (lower C, but much lower ESL, so self-resonant frequency much higher).

2. Ferrites - see comments above.

3. While there are differences between different isolated power + transceivers in terms of emissions and ease of mitigation, fundamentally they all share the same mechanism that generates the emissions and so all need similar design techniques.  Regardless of which part you use, you'll still need to have proper layout and EMC considerations - a weak design is going to have issues.  If the LTM2881HV-3 is working for you for other reasons, I would not suggest changing solely because of the emissions.  Following the guidelines/suggestions above, it should be possible to achieve a passing design.

Eric