The problem of Undervoltage flag (UVM) not being cleared of MAX22200 chip

Hi， I encountered an issue where I was unable to clear the Undervoltage Fault Flag bit of MAX22200 (PART NUMBER: MAX22200ETJ+) chip.  

(I referred to the official driver and initialization code) After powering on the MAX22200 and delaying for 200ms, the status register (0x00) read a value of 0x00040002 (Undervoltage Lockout (UVM=1)) after MAX22200 ENABLE. Then, I wrote the ACTIVE bit to 1 (read status=0x00040003 (UVM=1)), and configured the 8-channel configuration in a loop. After completing these tasks, I continued to read the status register in one loop, and the value of the status register was always 0x00040003 (UVM=1).

Obviously, I could not clear the UVM flag bit by continuously reading the status register (0x00); I have checked the hardware and VM voltage (VM=23.6V), but still cannot find the cause. I hope you can provide assistance.

    /* Shadow registers: InitEx programs CDR + low-side defaults before returning. */
    h->chan_side = MAX22200_SIDE_LOW;
    h->chan_drive = MAX22200_DRIVE_CURRENT;
    for (i = 0u; i < MAX22200_CHANNELS_CONFIG; i++) {
        h->ch_pair_mode[i] = local.ch_pair_mode[i];
    }

    MAX22200_CMD(h, GPIO_PIN_RESET);
    (void)MAX22200_SetTrigPins(h, false);
    HAL_GPIO_WritePin(h->cs_port, h->cs_pin, MAX22200_SPI_CS_IDLE_LEVEL);

    HAL_Delay(2000);

    if (h->en_port != NULL && h->en_pin != 0u) {
        HAL_GPIO_WritePin(h->en_port, h->en_pin, GPIO_PIN_SET);
    }
    /* Datasheet requirement: first STATUS read must happen after EN high and >=1 ms delay. */
    HAL_Delay(2);

    /* Step 1: read STATUS (command 0x00). */
    if (!MAX22200_RegRead(h, MAX22200_STATUS_REG, &status_before)) {
        return false;
    }
    max22200_log_init_status("step1(read-before-config)", status_before);
    if ((status_before & 0xFFu) != 0x02u) {
#if MAX22200_DEBUG_INIT_TRACE
        max22200_dbg("InitEx WARN: first STATUS low-byte is not 0x02");
#endif
    }

    /* Step 2: write STATUS (command 0x80 + payload). */
    status_reg = 0u;
    for (i = 0u; i < MAX22200_CHANNELS_CONFIG; i++) {
        status_reg |= max22200_field_prep(MAX22200_CH_MODE_MASK(i), (uint32_t)local.ch_pair_mode[i]);
    }
    /* Keep COMF masked on nFAULT during init, and activate the device. */
    status_reg |= max22200_field_prep(MAX22200_STATUS_FAULT_MASK(MAX22200_FAULT_M_COMF), 1u);
    status_reg |= max22200_field_prep(MAX22200_ACTIVE_MASK, 1u);
    if (!MAX22200_RegWrite(h, MAX22200_STATUS_REG, status_reg)) {
        return false;
    }
    if (!MAX22200_RegRead(h, MAX22200_STATUS_REG, &status_after_status_write)) {
        return false;
    }
    max22200_log_init_status("step2(read-after-status-write)", status_after_status_write);

    /* Step 3: configure channels one field at a time (no-OS style startup flow). */
    cfg_word = max22200_build_cfg_word(MAX22200_SCALE_FULL, MAX22200_HIT_MAX_VAL,
                                        MAX22200_TRIG_SPI, MAX22200_HIT_MAX_VAL,
                                        MAX22200_HIT_NO_TIME, MAX22200_DRIVE_CURRENT,
                                        MAX22200_SIDE_LOW, MAX22200_CHFREQ_DIV4);
    for (i = 0u; i < MAX22200_CHANNELS; i++) {
         if (!MAX22200_RegWrite(h, MAX22200_CFG_CH(i), cfg_word)) return false;
    }
     

    /* Keep all outputs off after initialization. */
    for (i = 0u; i < MAX22200_CHANNELS; i++) {
        if (!MAX22200_SetChannelOn(h, i, false)) {
            return false;
        }
    }

    h->chan_side = MAX22200_SIDE_LOW;
    h->chan_drive = MAX22200_DRIVE_CURRENT;

    HAL_Delay(2500);

    /* Step 4: read STATUS again (command 0x00). */
    if (!MAX22200_RegRead(h, MAX22200_STATUS_REG, &status_after)) {
        return false;
    }
    max22200_log_init_status("step4(read-after-cfg)", status_after);
    if ((status_after & 0xFFu) != 0x01u) {
        max22200_dbg("InitEx WARN: final STATUS low-byte is not 0x01");
        return false;
    }