Primary Side I²C Signal Integrity Issue (Intermediate Voltage Levels)

Hello Mert,

   Your suspicion that the bi-directional structure of the ADuM1250 being responsible for the side 1 V_OL=0.9V is correct.  This is normal and required behavior for the bi-directional isolator to be able to function.  See the functional description section on page 12 of the datasheet.  To summarize, in order to prevent the bi-directional isolator from forming a latch, on one side of the isolator the V_OL > V_IL which prevents that side's input from seeing the low output that the isolator is driving on that side.  Since this breaks the potential latch structure, it is ok for the other side to be unable to distinguish between an internally vs externally driven low and so for this side the V_OL < V_IL.  

  A common solution when side 1's high  V_OL is causing issues because it exceeds the V_IL of other devices on the bus segment is to reverse the direction of the isolator and to place the lower  V_OL side 2 on the problematic bus segment.  Because the ADuM1250 is bi-directional, there is no preferred direction for the data flow.

  I note that the rise time for the bus segment in your green trace appears to be rather slow compared to the bit timing.  In addition to reversing the direction of the isolator to have the lower V_OL of side 2 facing your FPGA,  you may want to consider decreasing the value of the pull up resistor for that segment so that the rising edge will be faster.

   Finally, note that the ADuM1250's minimum recommended supply voltage is 3.0V (Table 5, page 8) and its recommended to have its bus voltage swing be the same as the supply voltage.  This is important for side 2 whose V_IL/V_IH levels are ratioed to the supply voltage.  (Side 1's inputs are fixed within a voltage range).   The threshold levels for side 2 (0.3Vdd / 0.7Vdd) @ 3V will not be compatible with 1.8V logic (0.7*3 =2.1 > 1.8)  which will likely be a problem for your application. 

  A possible solution would be to consider using the ADuM1252 which supports logic supplies down to 1.71V and has a lower side 1 V_OL(max) of 0.69V. This may (or may not) be low enough to work with your FPGA; however, if not, you can still orient the part to have side 2 on the FPGA bus segment.  The ADuM1252ASA+ is directly pin and footprint compatible with the ADuM1250.

Eric

Hello Eric,

Thank you for the clarification. This explains the incompatibility I am seeing with the 1.8 V FPGA interface when using the ADuM1250 at 3.0 V, particularly due to the Side 2 VIH threshold levels.

Based on your recommendation, I will evaluate the ADuM1252 as an alternative, given its lower supply voltage support and reduced Side 1 VOL characteristics.

Thank you again for your support.

Best regards,
Mert