Back-to-Back Placement of Isolated Transceivers (LTM2881 + ISOW7840) on a 14-Layer PCB — Layout

Hi Salik,

   I can provide some additional guidance and general suggestions below; however, I also encourage you to open a technical support case here https://support.analog.com/en-US/technical-support/create-case-techsupport/ where a more detailed discussion of your particular design and tradeoffs can be more transparently discussed.

   First a general comment that the apparent conflicting guidance in the datasheets occurs because there are conflicting design goals which need to be balanced based on the details and constraints for the particular design.   Steps which mitigate one problem can make another worse. Finding the optimal balance requires trading off many factors as well as understanding the principles / reasons behind the different recommendations so that you can prioritize things appropriately for your particular design.

   Looking over your questions, I see there are at least three different points / issues to be considered in your design: isolation capability, thermal considerations and EMI performance.  These points will have interacting and potentially conflicting design goals that need to be balanced when working out your design.

   I would start by first understanding your application's isolation requirements and how they translate into creepage, clearance and distance through insulation requirements.  This will provide you with constraints that will guide spacing between the different voltage domains (in 3-D space).   These constraints will set a minimum spacing/distance.  Increasing the distance will improve the margin for the isolation and this is the reasoning behind datasheet comments such as your reference to the LTM2881's comment about "not placing copper between inner columns of pads".  Sometimes, depending on the actual application requirements, having properly placed copper in this space may be more beneficial than the isolation margin.   For example, this copper could be part of an EMI reduction strategy by forming a high-frequency "stitching" capacitance which bridges the isolation domain or it may provide additional copper area for heat spreading/dissipation.  

  One of your comments suggests that your isolation voltage requirements are only a few volts.  If this is the case, then isolation spacing and insulation thickness are really not much of a constraint and your standard design rules for trace spacing will likely be fine.

   For thermal considerations, you need to consider the thermal ambient of the board and other heat sources.  With the number of layers, there will likely be a good amount of copper present and so the board probably will have good thermal properties overall.   As a starting point, unless your application is operating at high ambient temperatures and/or there are lots of other heat sources on the board, its likely that no special design considerations will be needed here but you should still verify the operating temperatures to confirm this assumption,

   This then leaves the EMC considerations and potential for interactions between the two parts.  Isolated circuit structures inherently form dipole antenna structures with each side/voltage domain connected to the isolator forming one of the dipole antenna arms.  Note that from the antenna structure's perspective, all nodes/nets on a side of the isolator are connected together in a common mode sense.   The isolated power supply's switching action will impress a voltage across the isolation transformer's inter-winding parasitic capacitance which creates a current source to excite the dipole antenna creating radiated emissions.  In order to reduce these emissions you need to reduce the excitation source and/or reduce the effectiveness of the emissions path (antenna).  See my response to this EZ question:  emi-issue EZ question .

   You asked about a floating or connected copper patch providing electric-field shielding.   I would view these structures as part of a stitching capacitor which helps to short circuit the dipole antenna by providing a path for the common mode currents to flow.  This capacitor's plates are formed by carefully located and overlapping copper areas separated by the PCB's prepreg/fiberglass layers.  There are many possible capacitor structures which can be formed.  See the datasheets and Figures 7 & 8 of AN-1109 for examples.  How the copper is connected here will depend on the capacitor topology you're designing.  If the copper is floating then you effectively have two capacitors in series and if its connected to one of the voltage domains, then there is a single capacitor.  With the number of layers you have, forming some sort of multi-plate capacitor could be possible. Note that you'll want plenty of vias to connect the capacitor plates in inner layers to the layer with the isolator so that you minimize the series L.  

  Having multiple isolators will introduce multiple emissions sources and depending on how they are connected in the circuit, different voltage domains/antenna structures will be formed.  The EMC design principles will remain the same (short circuit the dipole with stitching capacitance and reduce the dipole arm size with series common mode filter impedance) but the details of how you implement these goals may vary depending on the antenna structures present.

Eric