ADM2561E layout design and restricted areas on PCB

Hello -opo-,

  These are good questions regarding system design tradeoffs.  In general your thoughts about what needs to happen are correct -  you're wanting to minimize the things that should be minimized and maximize the things that would be maximized.  The system design challenge is that you still need to make a realizable design subject to other constraints.  Thus, there is a limits to this optimization and so there are tradeoffs.  If the external constraints are stringent enough, the tradeoffs may become very difficult and in the worst case not resolvable (without relaxing a constraint).  Public forums like EZ are not really appropriate for this level of design discussion.    I can provide some additional comments / guidance, but I can't honestly give a specific simple answer to many of your questions.   You may want to consider opening a technical support case (https://support.analog.com/en-US/technical-support/create-case-techsupport/ ) where your particular design and constraints and tradeoff options can be more openly discussed.

Q1.  The red highlighted components are part of a filter to block the common-mode radiated emissions generated by the ADM2561E's isolated power supply.  Capacitor C12 provides differential filtering for the supply output and helps to minimize the ripple voltage which keeps the supply's regulation loop happy.  The two ferrites provide a common-mode impedance which limits the high-frequency common-mode current from flowing beyond the area of the pins, C12 and the ferrites.  The common-mode currents generated by the supply radiate due to a dipole antenna structure which is formed by the two voltage domains on either side of the isolated power supply. The red components form the isolated side's half of this dipole antenna.   By making this area as small as possible the antenna is detuned for the high frequencies that could cause issues and this is why we suggest making the red area small.  Due to physical part sizes and DFM rules, there is a limit on how small things can be.

Note that placing traces or copper around this 'hot zone' provides an alternative capacitive path for the high frequency common mode currents to flow to a larger area which could the re-form the antenna arm we were trying to remove with the ferrites.  Thus having some area around these parts is helpful.  The farther apart things are the greater the d between the parasitic capacitor plates and the lower the coupling & currents.  Farther is always better, but...   Often the design tradeoff here is to do as much as possible within otherwise constraints. 

One key point to focus on includes making sure to keep copper out from under the ferrites since that copper will form a short circuiting parallel capacitor.  Note that the physical structure of the ferrite with terminals on either end also forms a parasitic short circuiting capacitor.  Thus this can suggest a practical limit/distance when evaluating other parasitic capacitor structures that are in parallel since further reductions in the other parasitic capacitances will have a diminishing benefit.

Q2  The spacing between the two sides of the isolation barrier primarily depends on the required isolation voltage and operating environmental conditions for the application.   The isolation voltage and environment are considered by an applicable standard to result in the minimum distances between the conductive parts depending if the conductive parts are exposed or covered (and how they are covered).  For the evaluation board, it was simple to space the two copper planes by the width of the package which meant that the PCB was not a limiting factor in any isolation rating calculation.  

In some applications there may be other components which are also connected across the isolation barrier and their package/footprint may have a smaller creepage distance.  In that situation, this distance would limit the isolation voltage and so there is no benefit from an isolation voltage rating perspective to have a larger spacing.  There may be, however, other reasons why a larger spacing would still be desired.  For example, the isolation barrier forms an effective capacitor and this capacitance impacts ac leakage current.  Some applications may have an upper limit on allowed leakage current and so reducing this capacitance is beneficial.   Similarly, if the application needs to pass immunity tests where a common-mode transient current is injected into a port - a larger barrier capacitance could cause more of that current to flow through this portion of the board causing mischief either with the isolated transceiver or other circuits near by...

Q3 - as long as your spacing between the voltage domains meets your application's voltage requirements, conceptually what you're proposing is fine and this type of layout is used in many applications.   Note that this structure does potentially increase the parasitic coupling between the isolated side and the non-isolated side which may or may not be an issue when looking at EMC considerations (see other comments).

Q4 if your application has a lower required isolation voltage than that will reduce your minimum required spacing distances to meet voltage isolation requirements.  There may; however, be other reasons why you would want a larger distance (see other comments).

Eric